Engineer offers open-source verification language

Engineer offers open-source verification language
By Richard Goering, EE Times
November 20, 2001 (5:48 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0072

SAN JOSE, Calif. — Atsushi Kasuya, verification engineer at Juniper Networks Inc., didn't like any of the existing languages used for verification — so he wrote his own. Now Kasuya is offering his C-like language, Jeda, to the design community on an open-source basis under the GNU Public License.

Compared to Verilog, Jeda offers an ability to fork threads dynamically, use re-entrant function calls and take advantage of object-oriented programming. It promises superior garbage-collection support to commonly used C language dialects. Jeda is available at the www.jeda.org Web site.

Kasuya emphasized that Jeda is a personal project, not a Juniper Networks development. "I wanted to put all the good features of C, Java, Verilog and concurrent programming languages like Pascal into a single, formal programming language," he said. "I'm not so happy with existing languages in the industry because they're not o pen."

One problem with Verilog, Kasuya said, is that it's a "very, very static" language. With Jeda, he said, engineers can create dynamic threads any time they want. Multiple threads can be created, and each thread can run synchronously with various Verilog events.

"I can write a single function that does one transaction, and then I can fork off many of them as different threads and run them concurrently," Kasuya said. "Without thinking much, I can create very complicated test cases." (An example of Jeda code is presented below.)

Better choice

Kasuya believes Jeda is a better choice than SystemC because Jeda automatically handles garbage collection at the program level. "I strongly believe that putting everything in one big language is not a good thing," he said. "I would like to see a domain-specific language that does verification."

Jeda, in fact, is strictly a verification language — the actual design description should remain in Verilog, Kasuya said. Jeda links to Ver ilog through the programming language interface (PLI) and runs with a user's Verilog simulation. However, it supports the older Verilog PLI 1.0, not the current 2.0 version, because the later version wasn't available when Kasuya started his project.

Jeda code is compiled and linked to a dynamic library, and then loaded into the Verilog binary at run-time. This lets users run different tests without re-compiling Verilog images.

Kasuya acknowledged that Jeda does not provide an automatic way to generate test patterns. As such, he said, it's aimed more at ASIC verification than CPU verification. Jeda comes with what Kasuya described as a "simple debugger" that allows users to set breakpoints.

Limited support

Learning Jeda should be easy, Kasuya said. "I would expect someone who knows Verilog and C to take about one week to understand it and start writing code," he said. However, Kasuya noted, support is limited. "It's just myself," he said. "I hope someone will be interested enough to pick it up and offer support."

The Jeda Web site provides a user's manual and a binary for Solaris and Linux platforms. Users are asked to register at the message board and to report any bugs. The site notes that Jeda isn't seeking any financial donations and suggests that users who "feel generous" donate to the American Red Cross to support the victims of the Sept. 11 attacks.

Jeda language example

The following example is a simple testbench for a D-type flip-flop module. The first portset block defines the interface to the module. It has clk, D, and R_ as output, and Q as an input. The output has a skew value of 1, to avoid racing situations.

The program starts from the main() function as C. ff.clk.drive_clock() is an embedded member function for a port to drive it as the clock. It starts toggling with a given duty cycle. Then, it drives the FF reset pin, and toggles the D input every cycle, and checks if the Q output holds the expected value for 5 cycles. (The '.0' notation re presents the value of the port. Without it, it becomes the pointer to the port. )

Jeda becomes a module called 'Jeda_module' in Verilog with a user defined port on it. The Verilog testbench to run simulation can be found at the bottom. This can be automatically created by Jeda's template generator from the Verilog source code.

Jeda code

// ports interfacing to ff module
portset ff {
output clk drive posedge skew 1 ;
output D drive posedge skew 1 @ ff.clk ;
output R_ drive posedge skew 1 @ ff.clk ;
input Q sample posedge @ ff.clk ;
}

main() { // program always starts from main() function
bit p ; // 1-bit data

printf( " ff test started! " ) ;

ff.clk.drive_clock( 50, 50, 0, 0 ) ; // driving clk with #50, #50 duty

p = 1 ;
ff.R_.0 = 0 ; // drive Reset_ to 0
ff.D.0 = 0 ; // drive D to 0

@1(posedge ff.clk) ; // wait for on cycle
ff.R_.0 = 1 ; // clear Reset_
ff.D.0 = p ; // Drive D to the i nitial value

repeat( 5 ) { // toggle D input 5 times
@(posedge ff.clk) ;
if( ff.Q.0 !== p ) // testing the Q output propergates D input
error( "ff.Q output error, expect %d actual %d ", p, ff.Q.0 ) ;
p ^= 1 ; // toggle p
ff.D.0 = p ; // drive D with toggled p
}
printf( " ff test done! " ) ;
}

Verilog testbench to run simulation

module ff_test_top_module () ;
parameter SimulationCycle = 80 ;

reg CLOCK_reg ;
wire CLOCK = CLOCK_reg ;
wire ff_clk ;
wire ff_D ;
wire ff_R_ ;
wire ff_Q ;

jeda_module jeda (
.CLOCK(CLOCK),
.ff_clk(ff_clk),
.ff_D(ff_D),
.ff_R_(ff_R_),
.ff_Q(ff_Q)
);

// module ff under test
ff dut (
.clk(ff_clk),
.D(ff_D),
.R_(ff_R_),
.Q(ff_Q)
) ;

initial begin
CLOCK_reg = 0 ;
forever begin
#(SimulationCycle/2) CLOCK_reg = ~CLOCK_reg ;
end
end

endmodule