Meylan, France – February 22nd, 2010. In 2010, the Virtual Component Provider focuses their product offering on both their long-established know-how on Low Power designs for embedded memories and standard cell libraries. New architectures are released from the 130 nm technological process down to 40 nm LP with versions optimized for high speed.
Such Low consumption Libraries of memories and standard cells associated with their power regulators enable to satisfy the SoCs with most miserly power budgets:
- The Dual Voltage release of the Haumea spRAM generator meets the most demanding power budgets, thanks to its smart design for low dynamic power. At nominal voltage, Haumea DV is at least 50% less consuming than competitive memories claimed to be free. With its dual voltage capability the spRAM Haumea when operating at lower voltage moreover divides the power consumption by a factor of 1.8. The Haumea generator offers a flexibility in terms of instance capacities from 16 kb up to 512 kb. To ensure the best density while minimizing even further the power consumption at SoC level, the release of a regulator specifically optimized for Haumea is pending.
- HD-BTF DV, with a dual capability to operate in LV mode at lower voltage, also enables SoC designers to switch the voltage level back and forth with impressive dynamic power savings. Besides impressive power reduction, HD-BTF DV is also made for guaranteeing the lowest fabrication cost: density optimized cell layout, full routing enabled with only 3 metal layers, high density “spinner cell” logic.
- Thanks to an innovative cell layout, LC-BTF enables to divide the power consumption by a factor of 2 in comparison with the already celebrated density-optimized stem HD-BTF.
The library optimized for speed includes:
- The spRAM Rhea with an architecture optimizing the tradeoff between power Consumption and Speed. With the objective to address the needs of consumer applications, communications and networking markets, Rhea reaches up to 600 MHz in worst case for the 65 nm LP process. The Rhea generator offers a flexibility of instance capacities from 16 kb up to 256 kb
- The one port structure of register file Aura optimized for high density and high speed. With a performance of 600 MHz in worst case for the 65 nm LP process, Aura can typically be ideally used as a cache memory to benefit fully from the performance capability of speed optimized processors. The Aura generator is first available at nominal voltage and a Dual Voltage release is pending. The Aura generator offers a wide flexibility for words, bits per word, and capacities from 128 b up to 32 kb.
- Embedding the patent for “Shallow Trench Freedom”, the HS-BTF stem is up to 40% faster compared to the high-density stem HD-BTF. In any case HS-BTF is designed to enable stem mixing with either HD-BTF or LC-BTF, or both. Such mixing of stems results in the ultimate performances throughout the four stages of Data path Synthesis, Placement, Clock Path Synthesis and Routing, thereby enabling the best trade-off between density, speed and power for each design.
For more information on memories, click here.
For more information on standard cells, click here.
Due to the diversity of foundries and process nodes targeted, make sure to check the availability for any foundry and process.
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs. For more information about Dolphin, visit: www.dolphin.fr/sesame
