Lattice Announces Improved Synthesis and Power Optimization in CPLD Design Tools

ispLEVER Classic Version 1.4 Design Tools Feature Synopsys Synplify Pro and Improved ispMACH 4000ZE CPLD Fitter

HILLSBORO, OR, Aug 16, 2010  -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.4 of its ispLEVER(R) Classic design tool suite. The ispLEVER Classic design software has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH(R) 4000ZE CPLD fitter with improved power optimization.

Synplify Pro HDL Analyst provides designers a way to rapidly visualize high-level register transfer level (RTL) Verilog or VHDL. Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is the most efficient for the target CPLD. Finite State Machines (FSM), for example, are popular functions designed into CPLDs. FSMs are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings.

To minimize the dynamic power consumption of ispMACH 4000ZE CPLDs, the Classic 1.4 fitter now automatically enables the device's Power Guard feature for unused I/O and clock resources to avoid unnecessary internal switching. The ispLEVER Classic 1.4 software also includes improved features and educational material for the popular ispMACH 4000 CPLD family. The synthesis interface to the 4000 family has been upgraded with additional optimization control and a means to reference a Synplify Design Constraints (SDC) file for timing objectives. The ispLEVER Classic software Online Help has been expanded to make designing with Lattice CPLDs even easier and more efficient. Online Help now includes links to key technical "How To" topics for ispMACH 4000 architectural features and power estimation. A new "generic" schematic library manual describes logic symbols that are portable across SPLD and CPLD device families. The Classic 1.4 design software is bundled with the ispVM(TM) System 17.8 programming environment.

Designers can quickly download, for free, ispLEVER Classic for Windows, as well as the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules from: http://www.latticesemi.com/classic.

About the ispLEVER Classic Design Tool Suite

ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device completely through the design process, from concept to device JEDEC or bitstream programming file output. The ispLEVER Classic for Windows tool suite is a free download from the Lattice website at http://www.latticesemi.com/classic. Lattice customers can access the latest PLDs and FPGAs, including the MachXO(TM) PLD family, from the Lattice Diamond(TM) design software. Schematic/VHDL or Schematic/Verilog HDL Design Entry type projects created by ispLEVER Classic are forward compatible with the Lattice Diamond design software.

Third Party Tool Support

In addition to the tool support for Lattice devices provided by the downloadable versions of Synopsys Synplify Pro for Lattice and Active-HDL Lattice Web Edition, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL.

Pricing and Availability

The ispLEVER Classic 1.4 tool suite for Windows is available immediately for free. Classic 1.4 software is compatible with Windows XP/Vista/7 and operates as a 32-bit application.

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com