Virage nonvolatile memory to be built in logic process

Virage nonvolatile memory to be built in logic process
By Mike Clendenin, EE Times
February 25, 2002 (1:10 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020225S0032

TAIPEI, Taiwan — Memory designer Virage Logic Corp. is using a standard logic process to bring electrically alterable, nonvolatile memory with SRAM-like speed into the system-on-chip (SoC) arena, an advancement that will trim manufacturing costs without sacrificing on-chip performance, the company said.

Virage (Fremont, Calif.) is rolling out the embedded memory called Novea RAM on Monday (Feb. 25), touting it as a viable low-density alternative to flash or other types of integrated nonvolatile memory. The new architecture allows designers to combine what would typically be two manufacturing flows — one for logic and another specialized, less-advanced process for nonvolatile memory. Novea will first be available on Taiwan Semiconductor Manufacturing Co.'s 180-nanometer logic process, where it is currently undergoing qualification. But in the near future Virage expects other foundrie s to pick it up, including United Microelectronics Corp. and Chartered Semiconductor Manufacturing. The company also expects to march up and down the tech ladder so that Novea includes both 100-nm and 250-nm process nodes.

The Fremont, Calif.-based memory designer brought Novea to the generic CMOS process by implementing an approach to making nonvolatile chips first pitched about 10 years ago. Instead of using the more common stacked floating-gate structure, which means extra steps for a second poly layer and an additional dielectric layer, Virage said it used a "horizontal, folded control gate."

Typically, in flash and E²PROM processes, a "floating" gate sits below the control gate — isolated between two poly layers by two oxides with different threshold characteristics. The added cost comes from the extra masking steps needed to form the additional poly and insulating oxide layers.

Virage, by contrast, is using a one-poly-layer approach by unfolding the stacked ga tes. "We still have the floating gate above the structure but what we are now doing is using the well as a control gate and the coupling is happening from the well," said Krishna Balachandran, director of product marketing for Virage.

However, the drawback is that the design isn't as silicon efficient as higher-density nonvolatile memory, such as flash. This is not the market Virage is chasing, though. Instead, it is looking to initially attack E²PROMs and ROMs.

As the SoC era develops, Virage is hoping to cash in on a potentially lucrative niche market, in which low-density, lower-cost nonvolatile memory could be the choice for products ranging from encryption keys and chip IDs to the storage of configuration parameters in Bluetooth or 802.11 RF front-end chips.

Virage estimates that chunk of the market is approaching $2 billion. "Even if we replace the low end of this market, with the discrete E²PROMs and smaller, discrete ROMs, then we still have a sizable market share to go after," Balachandran said. "Even if we take 25 percent, it's a huge opportunity for moving nonvolatile memory onto the chip."

Novea RAM comes in a maximum size of 16 kbits and is designed for 1,000 store operations — at 100 milliseconds — and 1 million recall operations, at 10 microseconds. Balachandran said designers intentionally underplayed the store estimate to be on the safe side, but that based on early tests the chips may be able to handle upwards of 200,000 store operations.

The architecture includes two equally sized memory modules — one nonvolatile memory and one SRAM chip. Applications read from and write to the faster SRAM, using the nonvolatile chip only when data needs to be stored before the power switches off or retrieved when power is restored. The operating voltage for the SRAM chip ranges from 1.62 to 1.98 volts; the nonvolatile side uses 6 to 7.4 V.

Licensing fees will range from $100,000 to $500,000 and a volume-based royalty w ill also apply. A 128-bit memory block uses 0.15 mm² of space; in a chip ID, a 256-bit chunk would use less than 0.2 percent of the area on a 10 by 10-mm SoC, Balachandran said.