|
|||
Sequence Models IP for SoC Power Design Capability Within NanoCool Low-Voltage FlowSANTA CLARA, Calif. -- March 5, 2002 -- Sequence Design Inc., the SoC Design Closure Company, today announced the addition of IP power modeling to the company's NanoCool initiative, the leading flow for 100 nanometer low-power/low-voltage design. The NanoCool flow will leverage Sequence's leadership in RTL power, concurrent optimization, and extraction to partner with industry leaders to address the unique needs of designs at 100 nanometers and below (see 2/25 NanoCool release for additional details). Initial partners in the initiative include Silicon Metrics and Virtual Silicon. With the ever-increasing complexity of System-on-chip (SoC) design, power has become a major design concern. Intellectual property (IP) blocks such as digital-signal-processing (DSP) cores, embedded processors, memories, and analog and mixed signal blocks are integrated on the same silicon. Through Sequence's SoC PowerTheater suite, designers will be able to make decisions about packaging and power distribution early in the flow by leveraging high-quality IP power models. This tool suite will also perform power reduction and optimization, and thereby produce low-power designs in a shorter amount of time. While describing power behavior and creating power models manually is a time-consuming and error-prone process, the automated model generation process in PowerTheater allows the users to create power models quickly and efficiently. "IP modeling forms the foundation of low-power and low-voltage design," said Kevin Walsh, vice president of product management, Sequence Design. "Within our NanoCool flow, we will offer premier customers designing complex SoCs, as well as IP providers, a means to produce accurate and robust power models for IP blocks." Sequence provides a comprehensive methodology for SoC power management. The PowerTheater suite consists of Analyst for power analysis at the register-transfer level (RTL) and gate level, and Designer for pre-synthesis RTL power optimization. With the introduction of IP modeling, PowerTheater now enables designers to create detailed power models for IP blocks. The graphical user interface steps users through various modeling steps. While the suite supports all major industry standard library formats (Synopsys .lib, ALF and OLA), the modeling capability utilizes the rich syntax and versatility of the Advanced Library Format (ALF). A user is not required to have any knowledge of the ALF syntax in order to use the new IP modeling features. "Underneath the hood" it utilizes advanced constructs and modeling styles afforded by the ALF format. "With support for ALF models, Sequence's IP modeling capability can facilitate the creation of high-quality power models for complex IP blocks," said Dr. Wolfgang Roethig, chairman of the IEEE P1603 ALF Workshop and senior engineering manager at NEC Electronics Inc. "NEC Electronics will provide its customers with the required libraries and ALF models for the PowerTheater product, and we applaud Sequence's commitment to the industry's most accurate library modeling format." Availability
About Sequence
Sequence has worldwide development and field service operations. The company was formed through the merger of Sente, Inc., Sapphire Design Automation, Inc. and Frequency Technology. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections[tm] and Mentor Graphics' Open Door[tm] partnership programs. Additional information on the company can
be found at
www.sequencedesign.com
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |