Target Compiler Technologies Unveils New Tool-Suite for Multicore SoC Design

MP Designer™ tool-suite enables C code parallelization and platform generation for heterogeneous multicore SoC architectures

48th Design Automation Conference – San Diego, California, June 6, 2011. Target Compiler Technologies, the leader in application-specific processor (ASIP) design tools, today announced the upcoming release of a new tool-suite supporting the design of heterogeneous multicore systems-on-chip (SoCs). The tool-suite, which is called MP Designer, supports key design tasks such as the parallelization of sequential C code for multicore architectures and the generation of a communication fabric between multiple cores in SoC platforms. A pre-production version of MP Designer will be demonstrated in Target’s booth at the Design Automation Conference in San Diego next week. A full commercial release of the new tool suite is slated for early 2012. The first release is targeted to companies already using Target’s IP Designer™ tool-suite for ASIP design. Target is preparing for beta partner engagements now.

Today’s announcement underscores Target’s ambition to extend the reach of its EDA tools from the individual IP core level to the IP subsystem level.  Gert Goossens, Target’s CEO, said: “As evidence of the multicore revolution, more and more customers are integrating multiple ASIPs into larger SoCs.  Until now, the parallelization of application code and the design of the communication fabric between these multiple ASIPs remained a time-consuming and therefore often sub-optimal process.  Our new MP Designer tool-suite addresses these problems and brings the design of high-performance, low-power SoC platforms within easier reach.”

MP Designer adopts the idea of user-guided parallelization similar to the OpenMP® programming model used in general-purpose computing. As compared to OpenMP, MP Designer’s patented technology also supports heterogeneous multicore SoCs with point-to-point communication channels, allowing for efficient distributed memory architectures.  Global dataflow analysis techniques are used to check the correctness of the chosen parallelization.  MP Designer’s parallelization kernel operates as a C source-to-source transformation tool.  Graphical feedback about parallelization choices is produced in the form of task graphs.  MP Designer automatically adds all required software code for inter-processor communication and synchronization between tasks running on the different ASIP cores.  Furthermore, if needed, it can generate both RTL and simulation models of a communication fabric between the cores.

“MP Designer’s combination of user-guided parallelization with key architectural features such as heterogeneity and point-to-point communication, results in a powerful solution for embedded SoC design”, commented Dirk Lanneer, Vice President of Tool Development at Target.  “The source-to-source transformation concept and the task-graph visualization capability enable SoC designers to quickly evaluate alternative partitions of their C code such that an efficient load balancing between the different ASIP cores is achieved”, Lanneer added.

NXP Semiconductors is one of the companies that Target has been working with during the development of MP Designer.  Johan Van Ginderdeuren, Director of the CoolFlux DSP Licensing Business at NXP Semiconductors said: “We were truly impressed by the capabilities of Target’s MP Designer tool.  Using this new tool, a single-core implementation of our software-defined digital FM demodulator system on our baseband signal processing core CoolFlux BSP™ was transformed into a more power-efficient 3-core system, in only days of time.  Moreover, MP Designer has been proven to exploit our CoolFlux multi-core “Sea-of-DSPTM” communication framework.  A cycle-count acceleration by a factor 2.9 was obtained compared to a single-core implementation, and a speed-up of 21% compared to a pre-existing parallelized 3-core implementation.  While our licensable CoolFlux BSP is already designed for ultra-low power operation and can run digital FM demodulation in single-core mode, the resulting 3-core implementation allows for aggressive voltage and frequency downscaling, pushing the power envelope even further.”

Target will start an MP Designer beta test program with selected customers in August.  A commercial release of IP Designer is planned for early 2012. 

This announcement marks one of several announcements made today by Target.

About Target Compiler Technologies

Target Compiler Technologies (www.retarget.com) is the leading provider of retargetable software tools to accelerate the design, programming and verification of application-specific processor cores (ASIPs). Target's IP Designer tool suite is ideally suited for SoC designs in markets that mandate low silicon cost, low energy consumption, and flexibility to accommodate algorithmic changes. The tools have been used by customers around the globe to design SoCs for 2G/3G/4G handsets, cordless and VoIP phones, audio/video/image processing, infotainment and security for cars, DSL modems, DSL access multiplexers, wireless LAN, hearing instruments, and personal healthcare systems. Target is a spin-off of the Belgian nano-electronics R&D center IMEC, is headquartered in Leuven, Belgium, with North American operations in Boulder, Colorado.