MoSys And TSMC Extend Collaboration Agreement To 90-Nanometer-Based 1T-SRAM

SUNNYVALE, CALIFORNIA and HSINCHU, TAIWAN (March 29, 2002) - MoSys (NASDAQ:MOSY) and Taiwan Semiconductor Manufacturing Company (NYSE:TSM) today extended their long-standing 1T-SRAM^® collaboration agreement to include the 90 nanometer (nm) process node, bringing the industry's smallest bit cells to a broad market.

MoSys has already taped-out its 1T-SRAM and 1T-SRAM-R macros optimized for TSMC's 90nm technology. At 0.61u² (1T-SRAM) and 0.52u² (1T-SRAM-R), the cells are about half the size of the smallest announced 90nm SRAM cell. This small cell size enables early availability of 1T-SRAM memory designs with densities of 1.1mm² per megabit.

Under the agreement, the two companies will work together to offer MoSys' 1T-SRAM designs in TSMC 90nm technology, giving customers practical and cost-effective paths to system-on-chip (SoC) designs requiring high-density embedded memory. This latest agreement builds on the companies' partnership on all previous nodes from 0.25-micron to 0.13-micron.

"Our collaboration with MoSys on our 90nm process is consistent with our goal to accelerate the availability of options and value-added IP to the market," said Dr. Genda Hu, TSMC vice president of marketing. " Highly integrated designs require more embedded memory, so we are motivated to bring the smallest available CMOS memory cell into production quickly."

Mark-Eric Jones, vice president of marketing and Intellectual Property at MoSys, added, "We have already proven our 90nm 1T-SRAM bit cell concept at TSMC. With embedded memory representing the majority of die area on today's SoC designs and increasing every year, designers require the earliest availability of the best high-density embedded memory technology on advanced processes. It is the single most important enabler for their next generation SOC designs."

ABOUT TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company has one advanced 300mm wafer fab in production and one under construction, in addition to six eight-inch fabs and one six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 90-nanometer technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC please go to http://www.tsmc.com.

ABOUT MOSYS

Founded in 1991, MoSys develops, licenses and markets innovative memory technology for semiconductors. MoSys' patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM technology results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes. 1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in System on Chip (SoC) designs. 1T-SRAM technology is in volume production both in SoC products at MoSys' licensees as well as in MoSys standalone memories. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys website at http://www.mosys.com.

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Note for Editors:

1T-SRAM^® is a MoSys trademark registered in the U.S. Patent and Trademark Office. All other trademarks or registered trademarks are the property of their respective owners.