Celoxica upgrades its HW/SW co-design suite

Celoxica upgrades its HW/SW co-design suite
By Michael Santarini, EE Times
April 1, 2002 (10:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020401S0007

SANTARINI_MIKE The latest version of Celoxica Ltd.'s system-level hardware/software co-design and verification suite features support for ARM and PowerPC core-based programmable platforms. The DK design suite supports the design, validation, iterative refinement and implementation of complex algorithms in hardware. Built-in design entry, simulation and synthesis are driven by Handel-C, an ANSI-C-based language. Handel-C's extended concepts for timing, concurrency, flexible-width variables and resource allocation let software engineers and hardware designers implement complex algorithms efficiently in hardware.

In the latest version of the suite, DK1.1, Celoxica claims to have improved synthesis; enhanced area and delay analysis; improved VHDL output and Verilog output; sped simulation by 100x over the previous version; and added support f or Actel, Altera Excalibur and Xilinx Virtex II Pro devices.

To the co-design portion of the tool, Celoxica has added mixed-language support so users can call C/C++ functions from Handel-C descriptions and Handel-C functions from C/C++ programs. The refinement helps users decide which portions of a design should be rendered in hardware and which should be implemented in software. The mixed-language approach allows hardware designers to use C/C++ testbenches to verify Handel-C designs.

The tool can now output Verilog, in addition to VHDL and EDIF. It outputs structured Verilog and VHDL with the hierarchy of the Handel-C source code preserved so that hardware designers can debug the Verilog or VHDL output using conventional simulation tools. The HDL output can be targeted to either FPGA/programmable platforms or ASIC tool flows.

DK1.1 also has direct support for Exemplar Leonardo Spectrum, Synplicity Synplify and Synopsys FPGA Express. For simulation, it supports Model Technology's Mo delSim.

The EDIF output stage has been modified to shorten design time by producing more-readable signal names to aid in back-referencing from place and route tools to the original Handel-C source code, the company said.

A new technology mapper maps functionality to lookup tables rather than gates. That allows DK1.1's timing analysis tool to give designers an estimation of time and area before placement and routing.

The company has also added support for a wider range of programmable devices and programmable platforms, including Xilinx Virtex II Pro; Actel EX, 54SX, 54SX-A, RT54SX, RT54SX-S, ProASIC and ProASICPlus; and the Altera Excalibur EPXA10. The upgrade improves co-simulation support for the embedded processors shipped with Xilinx VII Pro (which uses the PowerPC core ) and Altera's Excalibur XA10 (which uses an ARM core).

Verilog co-simulation, via ModelSim, complements the existing support for VHDL. DK1.1 supports both functionally accurate and cycle-accurate co-sim ulation.

Further enhancements let users access processors and peripherals from the suite, featuring a Platform Abstraction layer (PAL) API and Data Stream Manager (DSM). Windows versions of the tool will be available this month, with Unix and Linux versions due in June. DK1.1 is priced at $35,000. The company licenses PAL and DSM separately.