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Xilinx enables flexible and low cost forward error correction solutions with IP cores optimized for Spartan-IIE FPGAsFEC solution ideal alternative for application specific standard products SAN JOSE, Calif., April 10, 2002 - Xilinx, Inc. (NASDAQ: XLNX), announced today the immediate availability of parameterizable forward error correction (FEC) LogiCORE products for use with its Spartan-IIETM FPGAs. The cores include a Reed-Solomon Encoder and Decoder, a Convolutional Encoder, two Viterbi Decoders, and an Interleaver/De-interleaver. When implemented in a low cost Spartan-IIE FPGA, the cores provide system architects and digital signal processing (DSP) designers with the ability to quickly build cost effective and flexible solutions. "Designers no longer need to concern themselves with being locked into a fixed FEC device that may become obsolete," said Per Holmberg, senior product marketing manager for IP Solutions at Xilinx. "The flexibility of these parameterizable cores, along with the cost-effective Spartan-IIE series, really changes the dynamics of system design, making it a preferred alternative to application specific standard products (ASSPs)." In addition to providing a competitively priced solution, the combination of the Spartan-IIE series with the FEC cores offers key benefits when compared to fixed function ASSP solutions. Designers can achieve tremendous flexibility both through the parameterization capability of the cores and through the programmability of the Spartan-IIE devices, allowing changes in specification late in the design cycle. Additionally, using Spartan-IIE FPGAs, designers can "future-proof" their designs. These low cost FPGAs support field upgradability, enabling their end products to be updated remotely. The combined solution of FEC cores and Spartan-IIE FPGAs allows designers to customize their products to meet their exact requirements, rather than being forced to pay for a fixed function alternative with unnecessary components. The newly released FEC cores include features that make them ideally suited for use with Spartan-IIE FPGAs. The IEEE 802-Compatible Viterbi Decoder includes best state initialization, resulting in improved performance with bursty data. The General Purpose Viterbi Decoder is available as a parameterizable netlist with a bit-error-rate (BER) option to monitor the error rate on the transmission channel. It also has both a serial and parallel architecture allowing the designer to prioritize area or speed for his design. A Convolutional Encoder is also available to support the transmit end of the link. The FEC offering also includes a high speed, very compact Reed-Solomon Encoder and Decoder and a Convolutional and Rectangular Block Interleaver/De-interleaver. License price and availability About Xilinx
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