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Siroyan debuts first high-performance DSP core, tools based on "next generation" architectureSRA328 outperforms any other DSP at given clock speed, claims Siroyan READING, UK, April 16, 2002 - Siroyan, the high-performance DSP IP company, today announces the availability of the first in its family of synthesizable cores based on the "next-generation" OneDSP architecture. Designated SRA328, this first soft core offers a fully-scalable performance level from 400 MMACs to 3200 MMACs at 200MHz, enabling it to target a wide range of applications from wireless communications to digital control and speech processing. In addition to the SRA328 core, Siroyan is also debuting its complete tool chain for application software development, which has been developed with the architecture and SRA328 soft core. The foundry-independent SRA328 is the first implementation of the OneDSP architecture and enables SoC (System-on-Chip) designers to deploy between one and eight execution-unit clusters in a single IP core - the actual number of clusters being determined by the designer when the core is instantiated. This enables the SRA328 core to offer unparalleled DSP performance and enables the optimisation of the soft core to suit performance, power and cost - according to specific SoC design requirements: Add clusters for more performance, or keep the die size down and deliver the performance for less cost. On a range of DSP algorithms, such as FIR, FFT and Reed Solomon, a 4-cluster instantiation of the SRA328 running at 200MHz outperforms any other DSP at a given clock speed, according to the company. The scalability of SRA328 is a key differentiating feature as it allows product life cycles to be extended since it allows application platforms to be developed with different levels of performance and by re-using the same software. A single soft-core delivery can be re-used in many applications and extends the product life of the core beyond that of today's hard-core products. This ensures an excellent return on investment in both the core and tools. As well as the number of clusters, SRA328 offers a choice of architectural configurations, memory subsystems and selectable, application-specific instructions. Each of these options can be selected using Siroyan's menu-based configuration system, which provides a wide range of performance points in the available design space, each of which is pre-verified in conjunction with the tool chain. According to Siroyan, this approach to configurability offers a distinct time-to-market advantage over hard-to-verify architectural extensions. The core uses a 64-bit AMBA High Performance Bus as the on-chip interconnect, providing a high bandwidth connection to memory, peripherals and other processor cores, and an integrated DMA device for memory-memory block moves, which implements scatter-gather capabilities and is capable of bit-reversed addressing. Also included is a debug interface, which connects via a Nexus 5001 interface to a debug adapter, offering Class 4-compliance at rates up to 100 MHz. This allows remote debugging from a desktop host. Instructions for SIMD Galois Field arithmetic can be included in this core as an optional item. These are particularly useful for Reed-Solomon codes and certain encryption algorithms. Power efficiency is achieved through a combination of architecture design and process optimisations, including the shutting down of clusters when not in use and support for a wide variety of power-down modes. Tools for application development Deliverables About Siroyan PR Contact: David CloseSiroyan and the Siroyan logo are trademarks of Siroyan Limited. All other company or product names are the registered trademarks or trademarks of their respective holders. |
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