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Princeton Technology Group Partners with Altera to Provide High-Speed I/O Evaluation BoardPrinceton Technology Group's Megalogic APEX II Evaluation Board Now Available to Altera Customers San Jose, Calif., April 24, 2002 -- Design engineers implementing telecommunications systems involving high-speed I/O interfaces can now reduce product design cycles and speed time-to-market with Princeton Technology Group's (PTG) high-speed evaluation board, Altera Corporation (Nasdaq: ALTR) announced today. As an Altera Consultants Alliance Program (ACAP) consultant, PTG will offer Altera customers the Megalogic Apex2A15 evaluation board to test their APEX™ II programmable logic device (PLD) designs that use LVDS, POS-PHY Level 4, RapidIO™, Hypertransport™, and other high-speed protocols. "The Megalogic evaluation board ensures thorough evaluation of the designs utilizing APEX II device's unique competitive features such as support for multiple, cutting-edge bus protocols and standards as well as numerous processing-intensive data path functions," said Hugh Durdan, vice president of technical services at Altera. "Our evaluation boards are extremely beneficial to Altera customers involved in designing next-generation SONET, wireless, and data networking applications," said Ted Altman, partner at PTG. "As an ACAP partner, our experience and knowledge of Altera devices allows us to provide a leading-edge evaluation board."
Altera created the Altera Consultants Alliance Program to give Altera's customers access to superior engineering consultants with an expert knowledge of Altera's device architectures and tools. These consultants have the proven ability and track record for accelerating complex PLD design schedules to facilitate a customer's time-to-market needs. More information about ACAP is available at http://www.altera.com/products/design_services/acap/acp-index.html. About Altera About Princeton Technology Group Editor Contacts:
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