MIPS multiprocessing core handles network duties

MIPS multiprocessing core handles network duties
By Loring Wirbel, EE Times
April 29, 2002 (10:09 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020429S0014

SAN JOSE, Calif. — MIPS Technologies Inc. has introduced a multiprocessing core optimized for network applications where cacheless interfaces to external SRAMs are preferred. The M4K core is the first to allow developers to insert user-defined instruction logic, extending specific instructions for proprietary header-analysis tasks while preserving compatibility with the MIPS instruction set.

The MIPS architecture has emerged as one of the standard instruction sets for control plane duties in network processing, emerging alongside ARM and PowerPC architectures as the favored choice for executive control. But in the data path, designers were looking for easy ways to implement multiple MIPS cores at a 32-bit level to augment a typical 64-bit control core. Mike Thompson, marketing manager for synthesizable cores at MIPS, said that MIPS' customers have developed many multi-CPU data path processors, leading the company to offer its own multiprocess ing spin of the midrange 4K family.

The M4K line is positioned between the uniprocessing 4K family on the low end and the enhanced uniprocessing 4KE series. The core is capable of 405-Dhrystone Mips performance in a 0.13-micron CMOS implementation. Like other members of the 4K family, it features a five-stage pipeline. The cacheless aspect of the core makes it a fully deterministic, single-cycle processor.

Conservative rules

Thompson said that, using relatively conservative CMOS design rules, it is possible to design eight-way or 16-way data path processors for applications such as advanced edge routers or access gateways. Multiple M4K cores could be implemented in true parallel-instruction fashion for storage-area network switches, in multichannel processing for line cards or digital subscriber line access multiplexers, or in pipelined fashion for multivariate routers doing complex header processing. The core supports semaphore instructions across multiple instantiations, for more eff icient interprocessor communications.

Several portions of the core block allow user implementation options. Multipliers can be implemented as fast arrays or small bit-serial blocks; register-set contexts can be set for one, two or four register sets; and an EC bridge with a link to local SRAM can be implemented. A decoder for MIPS 16e instructions can be added or left out; EJTAGs can be set with no probes, or with different combinations of hardware breakpoints; and a trace block can be added or left out, with options that include an on-chip trace buffer.

The EJTAG controllers can give designers a choice on debugging multi-CPU designs, Thompson said. Hardware breakpoints that operate across CPUs, for example, allow a breakpoint triggered in one core to halt other CPUs in the design instantly.

The M4K core typically dissipates 0.1 milliwatt per megahertz, and the core size can be as small as 0.3 mm² in 0.13-micron CMOS.

Early synthesizable designs are being introduced to partners in conjunction with this week's Embedded Processor Forum in San Jose, Calif. General availability of the core is scheduled for the third quarter.

More Embedded Processor Forum coverage.