eASIC® Awarded Six Patents for Very High Density Configurable Logic Technology

San Jose, California, April 30, 2002 -- eASIC Corporation, a provider of innovative configurable logic cores for System-on-Chip, today announced the award of six patents for very high-density configurable logic technology. These patents cover the concept of programmable logic cell array with mask-customized interconnection, as well as the segmented multi-layer routing fabric customized with a single mask, and additionally some unique elements of the eASIC technology.

With the award of these patents, eASIC has the Intellectual Property protection it needs to develop, sell or license eASICore for embedding in System-on-Chip and platform based IC designs. eASIC has already tested and implemented this technology in silicon (0.18, 0.15, and 0.13 micron).

These six patents and additional pending patents reveal a breakthrough ASIC technology that allows embedding high density configurable logic blocks in a fast, easy to implement and cost-effective manner. System-on-Chip and ASIC designers can take advantage of this efficient design technology that enhances time-to-market. eASIC's technology presents a new approach that resolves the issues of huge silicon area and circuit delay resulting from programmable interconnect in existing FPGA technologies.

Zvi Or-Bach, Founder, President & CEO of eASIC, and co-inventor of the patents noted:

"We believe that configurable logic technology is playing a very critical role in today's deep submicron IC designs. The soaring cost of semiconductor tooling and the complexity of deep submicron IC designs had driven the need for an efficient solution to cope with these challenges and meet the changing market requirements. We are very pleased that the US patent office has recognized our breakthrough technology and awarded eASIC with 6 very comprehensive patents. eASIC's strategy is to have its technology open to the ASIC designers community, relaying on the patent protection rather that build its business on confidentiality and trade secrets."

eASIC's proprietary eASICore technology allows configurable logic blocks to be embedded into user designs in a fast, easy to implement and cost-effective manner. This breakthrough technology combines SRAM Look-Up-Table cells with mask-customizable interconnection.

eASICore's technology takes advantage of the Look-Up-Table approach to logic implementation proven in FPGA technology, while avoiding the deficiencies of SRAM-programmable interconnect. This is made possible by eASIC's mask-configured, metal-to-metal interconnection. The result is significantly reduced silicon area and production cost. The performance of eASICore is much better than FPGA's, since the eASICore interconnect delay is significantly lower (10 to 100 times) than the SRAM-programmable interconnect used in FPGA technology. The eASICore delivers close to Standard Cell performance and density together with FPGA ease-of-design and time-to-market.

eASIC Corporation is pioneering a breakthrough approach of configurable logic cores for System-on-Chip and platform-based designs. Its configurable logic IP core, called eASICore, offers high performance and density with ease-of-design, rapid time-to-market and reduced development cost.

eASIC Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania.

Note: eASIC's technology is protected by US patents: US 6,194,912, US 6,236,229, US 6,245,634, US 6,331,733, US 6,331,789 , US 6,331,790 and additional pending patents. See legal.