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inSilicon Launches Triple-Speed Gigabit Ethernet MAC Subsystem for SOC Designs10/100/1000-Mbps Ethernet operation powers next-generation, high-speed communications products San Jose, CA, April 15, 2002 - inSilicon Corporation (Nasdaq: INSN) -- a leading provider of connectivity semiconductor intellectual property (IP), today announced the latest addition to their Gigabit Ethernet intellectual property product line, the Gigabit Ethernet MAC Subsystem (GMAC Subsystem). At 1-Gbps operations, the GMAC Subsystem serves the higher bandwidth data transfer requirements of high-speed, embedded communication system-on-chip (SOC) applications, and is backward compatible with the Ethernet standard for 10- and 100-Mbps operation. With the continued migration of Gigabit Ethernet from backbone networks to server provider and desktop market segments, designers are looking for Gigabit Ethernet solutions that are cost effective and easily integrated. The GMAC Subsystem meets those needs, providing the user with all components required to integrate a 10/100/1000 Ethernet port into an SOC. Built using inSilicon's silicon-proven Gigabit Ethernet MAC (GMAC) intellectual property technology, the GMAC Subsystem supports 10/100-Mbps and 1-Gbps data rates, special hardware filtering, VLAN, power management, and remote monitoring. GMAC also supports jumbo packets and control frames in Half- and Full-Duplex modes. This product is fully compliant with the IEEE 802.3x standard and provides the interface to IEEE 802.3z-specified (GMII) copper wire PHYs. GMAC, the major building block of the GMAC Subsystem, has been on the market since last year. One licensee, Acterna Corporation, a communications test company, licensed the GMAC through inSilicon's authorized design center partner, Memec Design, for implementation in Xilinx FPGAs. Licensing the GMAC technology enabled Acterna to complete a first-time working system in less than two months, shortening their time to market and conserving valuable engineering resources. In addition to inSilicon's GMAC block, the subsystem includes a FIFO layer and a programmable, descriptor-based DMA layer, eliminating the designer's need to develop these components so they can use that time for value-added system development. To ease system integration, the GMAC Subsystem can be easily bridged to any system bus via the VSIA PVCI standard DMA interface. "Many of our customers require more than a GMAC port, such as additional frame buffers and a DMA engine," said Fawzi Masri, product marketing manager of inSilicon Corporation. "With our expertise in reusable IP and this feature-rich product, we are providing more value to our SOC customers by reducing their design effort and shortening design time with an integrated and tested Gigabit Ethernet subsystem solution." Gigabit Ethernet MAC Subsystem Deliverables and Availability inSilicon's GMAC Subsystem is available today. Contact inSilicon for pricing information. About inSilicon "Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: The statements contained in this press release that are not purely historical are forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934. These forward-looking statements are based on management's beliefs as well as on a number of assumptions concerning future events made by and information currently available to management. Readers are cautioned not to put undue reliance on such forward-looking statements, which are not a guarantee of performance and are subject to a number of uncertainties and other factors, many of which are outside inSilicon's control, that could cause actual results to differ materially from such statements. For a more detailed description of the factors that could cause such a difference, please see inSilicon's filings with the Securities and Exchange Commission including its Annual Report on Form 10-K. inSilicon disclaims any intention or obligation to update or revise any forward-looking statements, whether as a result of new information, future events or otherwise. This information is presented solely to provide additional information to further understand the results of inSilicon.
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