Digital Blocks Extends its I2C Controller IP Core Family with Enhanced Capabilities & System-Level Features

The DB-I2C IP Core Family targets applications with full CPU off-load requirements and deep system-level integration capabilities.

GLEN ROCK, New Jersey --  January 8, 2013 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals requirements, today announces the extension of its DB-I2C-MS / DB-I2C-M / DB-I2C-S I2C Controller IP Core family, with the following enhanced system-level features & integration capabilities:

• CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon / Qsys interconnect fabrics
• DMA transfer between the I2C Bus & Memory (SDRAM / SRAM / FLASH)
• Direct interface to user Registers within ASIC / ASSP / FPGA, for Master/Slave transfer across the I2C Bus
• Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
• Enhanced SCL / SDA spike filtering capabilities
• Enhanced Repeated Start capabilities
• Control Unit which completely off-loads the I2C transfer from the CPU

The DB-I2C family contains the usual I2C compliant features: Multi-Mastering, Clock Synchronization, Arbitration, SCL held low by Slave, Repeated Start, 7/10-bit addressing, & General Call capabilities as well as 100 Kbs, 400 Kbps, & 1 Mbps I2C bus speeds.

The DB-I2C IP Core Family is offered as follows:

Model Number	Description
DB-I2C-MS-APB	I2C Master / Slave parameterized FIFO for targeted interconnect fabrics
DB-I2C-MS-AHB
DB-I2C-MS-AXI
DB-I2C-MS-AXI-Lite
DB-I2C-MS-AVLN
DB-I2C-M-APB	I2C Master-only parameterized FIFO for targeted interconnect fabrics. Master-only in VLSI space saving format.
DB-I2C-M-AHB
DB-I2C-M-AXI
DB-I2C-M-AXI-Lite
DB-I2C-M-AVLN
DB-I2C-S-APB	I2C Slave-only parameterized FIFO for targeted interconnect fabrics. Slave-only in VLSI space saving format.
DB-I2C-S-AHB
DB-I2C-S-AXI
DB-I2C-S-AXI-Lite
DB-I2C-S-AVLN
DB-I2C-S-RA	I2C Slave-only with Digital Blocks unique interface to user Registers

Price and Availability

The DB-I2C IP Core Family is available immediately in synthesizable Verilog, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at http://www.digitalblocks.com  

About Digital Blocks

Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals, Display Controller, Display Link Layer, 2D Graphics, Image Compression, Audio / Video processing, and High-Speed Networking / High-Frequency Trading Networking requirements.

Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; Fax: +1- 702-552-1905; Media Contact: info@digitalblocks.com ; Sales Inquiries: info@digitalblock.com ; On the Web at www.digitalblocks.com