Sonics' SMART Interconnect IP Supports Greater SOC Complexity and Accelerates SOC Design Cycles

New SiliconBackplane MicroNetwork Enables Hierarchical SOC Design, Lowers Power Consumption, and Enhances Functional Verification SMART Interconnect IP, the SiliconBackplane™ MicroNetwork version 2.2. The new version of the IP and accompanying development environment enables system-on-chip (SOC) designers and architects to dramatically reduce the time-to-market of products and entire SOC families. Key new features provide support for hierarchical SOC design, reduced power consumption, and more efficient functional verification, and combine to support higher SOC complexities while accelerating overall design cycle times.

SiliconBackplane MicroNetwork's new multi-backplane feature allows hierarchical subsystem partitioning of an SOC across multiple on-chip MicroNetworks. Sonics has also added a multi-cast feature that allows designers to send data to multiple IP cores across one or more MicroNetworks. Improved interoperability with third-party tools facilitates power analysis and optimization as well as the creation of interactive test benches for SOC verification.

"We've enriched the world's most advanced on-chip interconnect product so that even the most complex SOC projects we've seen can be created within a typical eight-month cycle; with derivative designs taping out every eight weeks," said Dave Lautzenheiser, vice president of marketing at Sonics. "Sonics has addressed several specific customer requests that extend the benefits of de-coupled SOC design and provide users greater control over interconnect bandwidth, power, and die area to attain the highest efficiencies of on-chip resources."

New MicroNetwork Features
With the multi-backplane feature, SOC designers can now incorporate multiple MicroNetworks into their chip designs to better architect de-coupled subsystems. This provides greater flexibility for the subsystem itself and the SOC as a whole. Multiple subsystems, each with an independent MicroNetwork clock frequency and data path width, can be connected in tree or fully connected topologies to isolate local data flows. This improves total system bandwidth while reducing SOC area and power consumption. The connections between MicroNetworks leverage the flexibility of the open core protocol (OCP) socket standard and do not require additional design work or glue logic.

Version 2.2 supports unmatched flexibility in optimizing the performance of write transfers, which are dominant in many networking applications. Designers can choose on a per-core or per-transfer basis whether writes should wait for an end-to-end response indicating write completion, important for device driver I/O transfers, or whether writes should respond immediately, which minimizes buffering requirements and results in higher total throughput.

The MicroNetwork graphical SOC development environment has been enhanced to include support for Synopsys' Power Compiler™. Using Power Compiler with MicroNetworks enables power consumption analysis and optimization at the register-transfer level (RTL) to achieve typical power reductions of 30 to 35 percent. The verification environment provided with the SOCCreator tool now uses Cadence's Test Builder™ to offer advanced run-time and batch-mode options for the creation of interactive simulation test benches. Sonics has also made numerous other enhancements to the MicroNetwork and its development environment to improve modeling, simulation and synthesis control.

Pricing and Availability
SiliconBackplane MicroNetwork version 2.2 is available for license immediately starting at $240,000 U.S. list.

About Sonics, Inc.
Sonics, Inc., the premier developer of MicroNetworks for "plug and play" integration of semiconductor intellectual property (IP) cores into system-on-chip (SOC) designs, is a privately held company in Mountain View, California. A Sonics MicroNetwork manages all communications between SOC subsystems, guarantees end-to-end performance, and ensures real-time quality of service. MicroNetwork technology enables flexible, platform-based SOC design through a robust development environment that uses an open standard core interface, the Open Core Protocol (OCP). Major semiconductor and systems companies have adopted Sonics' technology for SOC applications in the communications, networking and multimedia markets. For more information, see http://www.sonicsinc.com.