Digital Core Design announces D68HC11, HC11 legacy with all peripherals on board

Bytom -- May 31, 2013 -- Digital Core Design, IP Core provider and System-on-Chip design house, has introduced the D68HC11, which is fully software compatible with Motorola's HC11. Polish IP Core offers legacy architecture cycle compatible with original microcontrollers, like 68HC11E, 68HC11A, 68HC11D, 68HC11F1, MC68HC11K0 MC68HC(L)11K1, MC68HC(L)11K4, MC68HC11KS2, MC68HC711K4, MC68HC711KS2, MC68HC11KW1. The D68HC11 can be used as direct replacement, pin-to-pin compatible with the original HC11 MCU. Based on IP Core architecture improvement experience since 1999, Digital Core Design has introduced two options for the well-known D68HC11:

• Standard – with preconfigured MCU, where configuration is identical to the original HC11
• Optimized – an individual configuration with extra peripherals and additional custom blocks, required by the application [There's no need to waste time and money for unused features and wasted silicon]

What does it mean in real life/real design?  DCD's D68HC11 IP Core family is based on 3 major options: E, F, K – explains Jacek Hanke, CEO at Digital Core Design – they are devoted to the specific original MCU, but in contrast to it – every single one of them adds an extra value to the design, which means, it already has integrated on-chip major peripheral functions. There are asynchronous serial communication interface (SCI) and separate synchronous serial peripheral interface (SPI) included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Moreover, there's a self-monitoring, on-chip circuitry included, which protects D68HC11E against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides non-maskable interrupt, if the illegal opcode is detected. Two software-controlled power-saving modes - WAIT and STOP are available, to conserve additional power. These modes make the D68HC11 IP Cores especially attractive for automotive and battery-driven applications – adds Hanke.

The D68HC11 IP Core, can be also equipped with the ADC Controller. This allows to use an external ADC controller with standard ADC software. This extra design feature added in DCD's design makes external ADC's visible in the same way, as internal ADC's in the original 68HC11E Microcontrollers.

And last but not least, to make the D68HC11 even more adjustable, it's been equipped with a built-in, real-time, on-chip hardware debugger, allowing easy software debugging and validation. Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.

DCD's IP Core comprises also fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.

More information about D68HC11: http://www.dcd.pl/ipcores/59/      

More details about DCD's on Chip Debugger: http://www.dcd.pl/page/156/d68xx-docd/

 Key features:

• Cycle compatible with original implementation
• Software compatible with 68HC11 industry standard
• I/O Wrapper making it pin-compatible core
• SFR registers remapped to any 4KB memory page
• Two power saving modes: STOP, WAI
• Fully synthesizable
• Static synchronous design
• No internal tri-states
• Scan test ready