DCD Introduces Customizable LCD Controller

Bytom -- June 27, 2013 -- Digital Core Design, IP Core and SoC design house from Poland, has introduced a proprietary LCD controller equipped with 24-bit RGB output and synchronization. Moreover, like all DCD’s cores, the DLCD is provided as a fully synthesizable RTL therefore can be implemented in both ASICs/SoCs and FPGAs.

Whereas LCD technology is the most popular in digital imaging, DCD’s con-troller works smoothly also with CRT displays. Pixel data has an 8-bit resolution and a 24-bit RGB out-put is generated using external LUT with defined color palette. – Our LCD core is controlled by the CPU, which enables usage of an external data memory to display data – explains Tomek Krzyzak, VCEO at Digital Core Design – so all the parameters are configurable through the CPU register interface.

The core itself was designed to be used with DCD’s DP80xxx series of MCUs, which means, that it can be easily bundled with e.g. DQ80251, the world’s fastest 8051 MCU, as long as the other 51s like the DQ8051, DP8051 or DP80390 IP Core. All parameters are configurable by CPU but there is also capa-bility for setting parameters by modification constants in a source file. There’s no need to waste silicon resources for unused features and constant settings  The display controller is perfect for MCU based applications, where static graphic data is displayed using LCD/TFT matrix or e.g. CRT monitor.

Like all DCD’s IP Cores, the DLCD is provided as a fully synthesizable RTL so can be implemented in both ASICs/SoCs and FPGAs.

More information at: http://www.dcd.pl/ipcore/133/dlcd/ 

Datasheets and specs at: http://www.dcd.pl/workspace/documentation/alt/dlcd_ds.pdf

Key features:

• 24-bit RGB output, 8-bit pixel with external LUT for color palette
• Configurable screen parameters
• Configurable memory data bus width
• Wait states for memory access
• Pixel clock divider
• Display data copying without CPU access
• Display data accessible for CPU as external data memory
• Fully synthesizable
• Static synchronous design and no internal tri-states