Real Intent brings clock checking to formal tool

"Today's SoCs and communication designs commonly have multiple clock domains, which means different parts of the design are being clocked at different rates," Narain said. "To ensure reliable data path across these interfaces, designers have to employ guidelines that have to do with structural as well as logical design."

He said that the feature, which will be available in version 4.0 of Verix this summer, ensures that the structural and logical guidelines are followed.

Narain explained how it works: Users feed the tool RTL code, either Verilog or V HDL, and identify clocks and resets in their design. Then, the tool automatically identifies the clock domains and the hazards for signals crossing those domains. The absence or presence of synchronizers at the clock domain boundaries also are identified. After running the analysis, the feature advises designers about what assertions they need to place into their designs to formally verify that the data transfer is implemented effectively.

Version 4.0 with the assertion-based formal clock intent verification is being used successfully at beta customer sites, Narain said.