Tabula Announces Availability of Stylus Compiler Version 2.7.1

August software release features SystemVerilog support, DSP IP and new design examples

SANTA CLARA, Calif. -- August 2, 2013 – In a continuing move to help make network infrastructure systems more responsive to applications’ dynamic needs, Tabula, Inc. announced today the availability of version 2.7.1 of its Stylus® compiler supporting its ABAX®2 P-Series of 3D programmable logic devices (3PLDs).  Stylus 2.7.1 further eases design of complex high-bandwidth systems with the addition of support for the hardware description and verification language SystemVerilog. To help accelerate the development of high-performance applications, the software also features new design examples showing how to utilize Spacetime® technology with its many-ported memory blocks and how to build high-performance, small-footprint finite state machines (FSM) using ROM structures. This release also includes a 1 giga-samples per second Fast Fourier Transform (FFT) IP core demonstrating the digital signal processing potential of the ABAX2 family of devices.

The new capabilities and design kits introduced in the Stylus 2.7.1 release include:

• SystemVerilog support: Addressing the increasing customer demand for a combined design and verification language, Tabula’s Stylus compiler can now process code written following SystemVerilog syntax. This capability not only increases the supported application domains, but also prepares the path for the future use of assertion-based design debug.
• Soft IP cores: A high-performance 1 Gsps FFT IP core is now available on the Tabula IP Management System (found at http://customer.tabula.com). This core can be configured for transforms of 1K, 2K, 4K, 8K, 16K or 64K points.  
• Design examples:
• A 12-ported RAM block design example showing how to express many-ported memory blocks and manage port access ordering in a Spacetime-based fabric.
• A ROM-based finite state machine design example to illustrate how Spacetime enables new approaches to sequential logic design ideally suited to high-performance datapath systems.

More about Stylus compiler

Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime architecture, unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density.  In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.

Availability:

Stylus version 2.7.1 is available now for download at customer.tabula.com at no-charge.

About Tabula:

Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com