Denali's on-chip bandwidth processor core targets memory efficiency

Denali's on-chip bandwidth processor core targets memory efficiency
By Semiconductor Business News
May 29, 2002 (12:49 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020529S0024

PALO ALTO, Calif. -- Denali Software Inc. here said it has developed an on-die programmable memory controller core to allow system-on-a-chip designers get much higher memory efficiency in their products.

Called the Databahn Bandwidth Processor, the intellectual property (IP) design core can adjust the memory access for different and multiple processor clients that may be on the system-on-chip product. Denali officials said that up to now SoC designers essentially had to "hardwire" the memory controller interface to handle each separate processor client on the chip, foregoing the greater performance that could be obtained by adjusting the memory access in real time to get maximum throughput.

Denali has expanded its previous configurable memory controller core to include the new programmable feature, said Mark Gogolweski, vice president of engineering of the company. This is done by allowing the SoC designer to add up to 30 on-die registers t hat can be programmed in real-time through software in chip operation.

With the technology, designers can selected a range from 2-bit to 32-bit registers, based on Denali's database of memory chip characteristics and features for optimum interface with the particular processor client core on the SoC design.

Until now, system-on-chip designers spent considerable time specifying precise memory controller functions to get the exact bandwidth and priority data access patterns needed. Kevin Silver, vice president of marketing, said the Databahn Bandwidth Processor core simplifies the design by matching the best suited memory, whether SDRAM, DDR, reduced latency DRAM or fast cycle RAM which the unique operating characteristics of different types of processor cores on the SoC.

Silver said the programmable function can increase memory efficiency to 90% over 70%-to-80% normally achieved for SoCs.

Denali delivers synthesizable RTL (register transfer language) code that designers can use immediately. The Databahn Bandwidth Processor IP is available now.

By Jack Robertson of EBN, a sister publication of Semiconductor Business News.

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