TransEDA Enables Property Driven Verification Methodology with New Release of its VN-Property DX Dynamic Property Checker

New Graphical Capture Capability Combines the Power of Properties with Point-and-Click Ease-of-Use

LOS GATOS, Calif. (U.S.A.) -- June 3, 2002 -- TransEDA PLC, the leader in ready-to-use verification solutions for electronic designs, today announced a new graphical capture capability in its VN-Property DX dynamic property checker that combines the power of properties with point-and-click ease-of-use. The company also announced that the latest release of VN-Property DX supports the industry-standard Accellera Sugar property language and reads simulation logs in the popular Vector Change Dump (VCD) and open Fast Signal Database (FSDB) formats, for even easier integration into existing verification and debug flows. In a separate announcement, TransEDA announced integration of VN-Property DX with the popular Debussy knowledge-based debug system from Novas Software.

The VN-Property DX dynamic property checker verifies properties from architecture to system level during simulation. It accelerates verification of complex systems by measuring the effectiveness of simulation against standard or design-specific properties. Users have found that developing properties for complex behaviors is easier than making an equivalent checker or assertion in HDL.

"Adoption of a property-driven verification methodology from the architecture level through system integration can significantly reduce overall verification time," said Tom Borgstrom, vice president of marketing, TransEDA. "With this latest release of VN-Property DX, we've embraced the open Accellera property language standard, enabled easy integration in existing flows, and provided a best-in-class debug solution. The new graphical capture interface will make the product widely accessible. Because it is so much faster and easier to use properties to specify design intent than to use other methods, a property-driven methodology will usher in a new era in verification productivity."

"I'm very pleased to see early adoption of Sugar in the marketplace," said Dr. Yaron Wolfsthal, Manager of Formal Methods at the IBM Haifa Research Lab. "TransEDA has taken the path of delivering a simulation-based property checking solution to the design verification community, which in my experience is a practical and powerful approach."

New Features of VN-Property DX Speed Design Verification
 

• Graphical Capture Interface: The new graphical interface in VN-Property DX enables properties to be easily captured, viewed and manipulated. Once captured, properties will be saved as editable Sugar files. Because properties can be rapidly captured and understood, both power and novice users can realize the benefits of a property-driven verification methodology even sooner.

• Support for Industry Standard Property Language: Many leading EDA vendors and users have pledged support for the Accellera Sugar formal property language from IBM. The new version of VN-Property DX supports this industry standard language to promote tool interoperability and enable property re-use.

• Support for VCD and FSDB Simulation Log Formats: Many designers capture simulation logs in standard VCD or Novas FSDB formats for simulation debug. This release of VN-Property DX enables these existing simulation logs to be used to drive dynamic property checking. Using the same log file for both simulation debug and dynamic property checking simplifies the task of integrating VN-Property DX in existing verification flows.

• Support of Novas Debussy for Design Debug: Support for Novas Software's Debussy knowledge-based debug system enables engineers to significantly decrease time spent debugging property violations. When an engineer finds properties violated in simulation with VN-Property DX, those violations can be immediately and seamlessly debugged using Debussy.

About Verification Navigator

The VN-Property DX dynamic property checker is part of TransEDA's Verification Navigator integrated design verification environment, which features tools that enable IC designers to manage and shorten verification time. In addition to VN-Property DX, Verification Navigator includes VN-Check� configurable HDL checker, VN-Cover coverage analysis, VN-Cover Emulator coverage analysis for hardware-assisted verification, VN-Optimize test suite analysis, and VN-Control application-specific test automation. Verification Navigator supports all leading Verilog, VHDL, and dual-language simulators and is available on the Solaris, HP-UX, AIX, Linux, Windows NT, and Windows 2000 platforms.

Pricing and Availability

VN-Property DX version 2002.07 featuring support for the Accellera Sugar property language, the VCD and FSDB log file formats and Novas Debussy will be available in July 2002. The new graphical capture interface will be available in Q3 2002. VN-Property DX is independent of design language and pricing starts at $15,000 (U.S.) for an annual subscription license. For more information on VN-Property DX, visit www.transeda.com/vnpropertydx .

About TransEDA

TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets ready-to-use design verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models and properties for advanced microprocessors and standard bus interfaces.

TransEDA's design verification software performs application-specific test automation, configurable HDL checking, dynamic property checking, code and finite state machine (FSM) coverage analysis, and test suite analysis. TransEDA's tier-one customers include 18 of the world's top 20 semiconductor vendors.

For more information, visit www.transeda.com or contact TransEDA at 985 University Avenue, Los Gatos, Calif. 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, e-mail info@transeda.com.

Note: TransEDA and Verification Navigator are registered trademarks and VN-Property DX, VN-Check, VN-Cover, VN-Cover Emulator, and VN-Optimize are trademarks of TransEDA. Novas Software and Debussy are registered trademarks of Novas Software, Inc. All other trademarks are property of their respective holders.