DCD's HDLC/SDLC controller aims telecommunication

Bytom -- December 2nd, 2013 -- Digital Core Design, an IP Core provider and a System-on-Chip design house, has introduced its latest soft IP Core, the DHDLC. It’s been designed to control HDLC/SDLC transmission frame and optimized for great variety of 8, 16 and 32-bit MCUs. Same as all other DCD’s IP Cores, the DHDLC is a technology independent design, therefore can be implemented in both, ASIC and FPGA.

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, no matter if it’s 8-, 16- or 32-bit microcontroller. The greatest advantage of this IP Core is the possibility to save MCU time wasted for handling HDLC/SDLC features, like bit stuffing, address recognition and CRC computation. To enable even more productivity, the DHDLC has an implemented FIFO buffer, for both receiver and transmitter. – We’ve designed the DHDLC IP Core, because… our customers asked us to do it so many times – explains Jacek Hanke, DCD’s CEO. Configurable core parameters and adjustable CPU interface are a must be in this project.

The DHDLC IP Core is fully synchronous with one clock domain design. All parameters are configurable by CPU, but there is also an another option. One can set all the parameters by modification constants in a source file. Thanks to it, there’s no need to waste silicon resources for unused features and constant settings.

DHLC’s Key Features:

• Two separate receiver and transmitter interfaces.
• Two separate, configurable FIFO buffers for receiver and transmitter
• Bit stuffing and unstuffing
• Address recognition for receiver and address insertion for transmitter
• Two or one byte address field
• RC-16 and CRC-32 computation and checking
• Collision detect
• Byte alignment error detection
• Programmable number of bits for idle detection
• NRZI coding support
• Shared flags, shared zeros support
• Pad fill with flags option
• Transmitter clock generation
• 8-bit, 16-bit, 32-bit CPU interface
• Interrupt output for handling control flags and FIFOs’ filling
• Configurable core parameters

More information at http://dcd.pl/ipcore/670/dhdlc/

Information about Digital Core Design:

Digital Core Design is a leading Intellectual Property (IP) Core provider and a System-on-Chip (SoC) design house. The company was founded in 1999 and since the early beginnings has been considered an expert in IP Core architecture improvements. Thousands of customers became convinced by our unique solutions and billions of people worldwide use our technology in USBs, MP3 players, mobile phones and many other applications.

The innovativeness of DCD's IP solutions has been confirmed by over 500 licenses sold to over 300 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, OSRAM, GENERAL ELECTRIC, SILICON GRAPHICS, RAFAEL, SAGEM and GOODRICH.

More information: http://dcd.pl/page/147/about/