Adelante Technologies and Axys Design announce Saturn-Based JPEG200 virtual prototype

AXYS Design's MaxSim Tool and Adelante's IP Library Allow Virtual Prototyping of  JPEG200, 802.11, 3G, VoIP and Other Saturn-Based Multi-Processor Applications

JUNE 10, 2002, DESIGN AUTOMATION CONFERENCE, NEW ORLEANS, LA. -- Adelante Technologies™ and AXYS® Design Automation jointly announced the development of a virtual prototype of Adelante's JPEG2000 reference platform which includes Adelante's SaturnTM DSP Core, an ARM920T core, and Adelante's highly optimized Wavelet and Ebcot co-processors. This reference platform is implemented in AXYS Design's MaxSim™ prototyping environment and enables designers to do early-stage software development and debugging of system software, and evaluate system-level hardware/software trade-offs.

The JPEG2000 reference platform is just one example of the type of high-performance, multi-processor designs that can be achieved by using the Saturn DSP Core in conjunction with an ARM (or other RISC) processor and Adelante's highly optimized application specific co-processors. Additional Saturn-based applications that can be designed using MaxLib™ virtual prototypes include 802.11, 3G, VoIP and others.

Adelante's high performance, low power Saturn™ DSP core executes up to 440 MACS, has a die size of only 0.5mm2, and consumes 0.25 mW/MHz. (0.18 micron process) which makes it ideal for baseband and speech processing in 2.5G and 3G mobile phones as well as digital servo control.

AXYS Design's MaxSim environment allows system-on-chip (SoC) designers to create and simulate prototypes of complete application platforms for the purpose of trade-off analysis, hardware verification and software development and verification. By using MaxSim, designers can verify complex multi-processor systems-on-chips in a fraction of the time required for conventional event-driven, HDL-based simulations. MaxSim offers the high simulation speed without sacrificing the timing accuracy essential for the development of real-time embedded applications.

According to Rob Woudsma, Adelante's chief technology officer, "The majority of wireless handsets on the market today include both a DSP and an RISC processor. Increasingly, both processors are being integrated into a single system-on-chip to generate the extra processing power required for 2.5 and 3-G phones while simultaneously reducing power consumption and cost. Historically, multi-processor SoCs have been extremely difficult to verify because standard event-driven HDL-based simulation models are too slow to simulate even a few seconds of system operation.

"Adelante and AXYS have solved this problem by including the new Saturn DSP core and Adelante co-processor models in AXYS Design's MaxLib library," Woudsma explained. "The Adelante Saturn and co-processor cores can now be easily combined with those of ARM®, MIPS® and other processor providers for software development, multi-core debugging and verification, months before SoC silicon exists. These virtual multi-processor systems are easily integrated into a variety of standard hardware and software development environments offering a smooth hardware/software development flow."

"Time-to-market and system aspects of new designs are the dominant factors for the success of our joint customers," said Vojin Zivojnovic, president and CEO of AXYS Design. "With the release of Adelante's complex JPEG2000 virtual platform and the availability of Adelante's Saturn and coprocessor models in AXYS' MaxSim prototyping environment, Adelante and AXYS have pushed the envelope of pre-silicon SoC design and embedded software development a significant step further."