Revolutionary New Databahn Core Solves Memory Bandwidth Bottleneck for SoC Designs

Denali's AMBA-compatible core provides system architects configurable, multi-port bandwidth allocation for optimal memory access by on-chip processing units

Palo Alto, CA – June 10, 2002--Denali Software, Inc., the leader in memory system design and verification, today announced its Databahn™ core for SoC bandwidth allocation, the first intellectual property core to dramatically reduce the time designers spend on developing and testing SoC memory systems. The configurable and programmable core manages and optimizes the memory access of multiple on-chip computing clients to the finite bandwidth of off-chip DRAM memory.

Today's SoC designs incorporate various RISC processors, DSP's, and dedicated processors, all of which require high-bandwidth access to off-chip memory. Some access memory via on-chip interfaces such as AMBA® technology from ARM, while others interface memory via dedicated ports. SoC designers spend considerable time designing systems to allocate off-chip memory access to the various on-chip processing units--all based upon the unique bandwidth and latency requirements of individual processing units. The task is further complicated by the need to adjust the memory access to the processing elements during the design process, and the need to support new and emerging high-speed DRAMs such as DDR-SDRAM, FCRAM, and RLDRAM.

"Databahn resolves all of these conflicting requirements," said Mark Gogolewski, Chief Operating Officer and VP of Engineering at Denali. "This new Databahn core contains a completely configurable multi-port arbitration unit, integrated to a configurable DRAM memory controller. The solution allows dynamic and granular trade-offs between high-priority, low latency requests and overall optimized bandwidth. Furthermore, Databahn is supported by online performance analysis tools at eMemory.com where system architects can prove out their SoC approach with a variety of the new and different DRAM memory types."

"AMBA technology has become a de facto standard for on-chip interconnect for SoC designs," said Jonathan Morris, ARM Infrastructure Program Manager. "AMBA technology enables designers to reduce time-to-market by reusing readily available IP blocks. Having an IP block with a configurable number of ports handling multiple buses also helps reduce time to market by offloading this task from the designers."

"Today most SoCs have multiple intelligent on-chip clients--RISC processors for control as well as DSPs for time-critical data traffic," said Mike McKeon, Denali's Databahn Program Manager. "Our Databahn core for SoC bandwidth allocation apportions each port the optimum amount of bandwidth while squeezing the maximum throughput between all ports and the off-chip memory."

"Building custom solutions to arbitrate off-chip memory resources poses a number of problems," said McKeon. "Custom logic is expensive and risky to develop and test, requires expert knowledge of the DRAMs and controller logic, and is usually not flexible enough to support changes or optimizations throughout the design process. Databahn provides designers with silicon-proven cores that easily integrate into their SoC design, and offers the configurability to ensure high-performance in real-world SoC designs."

"Today most SoCs have multiple intelligent on-chip clients--RISC processors for control as well as DSPs for time-critical data traffic," said Mike McKeon, Denali's Databahn Program Manager. "Our Databahn core for SoC bandwidth allocation apportions each port the optimum amount of bandwidth while squeezing the maximum throughput between all ports and the off-chip memory."

About Databahn
Databahn is a highly integrated, market-focused solution for high-performance memory system development. Silicon-proven cores for memory control and on-chip bandwidth allocation are supported by an online infrastructure at Denali's eMemory.com site. System architects use a browser-based GUI to configure and validate the Databahn cores for application-specific performance. Designers then use the web-based interface to automatically generate and export the synthesizable core and related verification IP for their particular design and verification environment. To ensure compatibility with all the latest high-speed DRAM memory technologies, the configuration process is tightly integrated with a database of more than 4500 memory components, including the latest DDR-SDRAM, FCRAM, and RLDRAM components.

Price and Availability
Databahn cores are available immediately; contact sales@denali.com for pricing details.

About Denali Software, Inc.
Denali Software Inc. is the world-leading provider of solutions for memory system selection, design, and implementation. Denali's eMemory.com is the most comprehensive and up-to-date source for memory component information, and houses an online infrastructure for its memory selection, memory controller IP, and memory simulation products. Denali also offers memory market research services, which provides customers with the most unbiased and forward-looking information on the technology and economics of semiconductor memories. More than 400 companies worldwide use Denali's tools, technology, and services to plan and develop memory systems for communications, consumer, and computer products. For more information, contact Denali at www.denalisoft.com, or call (650) 461-7200.

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