|
||||||||||
NurLogic Implements 4.8GHz Phase Locked Loop Into AMD's Eighth-Generation ProcessorsSAN DIEGO – June 10, 2002 – NurLogic Design, Inc., a developer of high bandwidth connectivity solutions, today announced the successful implementation of their high-performance Phase Locked Loop (PLL) [analog intellectual property (IP)] into the AMD Opteron™ and eighth-generation AMD Athlon™ processors. NurLogic and AMD announced the initial agreement in June 2001. NurLogic delivered an advanced 0.13-micron Silicon on Insulator (SOI) PLL to AMD's exacting standards for their forthcoming microprocessor family, offering the added benefit of increased performance. The two companies worked closely together during the last several months to design, validate and test this advanced analog solution. The design challenges to create a PLL such as this are extensive. As CPU frequencies increase to multiple Gigahertz, PLLs must be designed with the lowest possible jitter. Additionally, a process optimized for high-speed digital logic makes it difficult to achieve optimal analog performance. As part of a solution to address these issues, NurLogic developed an innovative PLL architecture to overcome these difficulties. On-chip regulators compensated for the noise environment of large digital devices. When processing was complete, NurLogic and AMD's engineering teams worked together to validate a first silicon success. "We are extremely proud of our eighth-generation processor design, and extremely pleased to have a vendor like NurLogic that we can count on to deliver," said Bruce Gieseke, Senior AMD Fellow, Computation Products Group. "Not only did NurLogic work diligently with us throughout the design and validation phases, they designed a PLL that exceeded our expectations." NurLogic's extensive analog expertise was an important component in addressing AMD's unique PLL requirements. NurLogic's advanced patent-pending architecture enables optimal operating performance with minimal jitter. NurLogic offers a full line of high performance PLLs ranging from 266 MHz to 4.8 GHz. "The design of PLLs that are to be deployed in a hostile mixed-signal environment is not for the faint of heart, but NurLogic has mastered the art," said Thomas H. Lee, professor of Electrical Engineering at Stanford University. "Time and again, NurLogic has proven their ability to innovate brilliant solutions to exceptionally difficult problems, rising to the challenges posed by scaling trends that are highly unfavorable to analog performance. The thoroughness with which NurLogic approaches the issue of sensitivity to process variation has ensured consistent first-silicon success. This is the "A team" of PLL designers!" According to Michael Brunolli, chief technical officer for NurLogic Design, Inc., "Our goal is to provide great technology and customer satisfaction. We're glad that we were able to help AMD at such a critical time. This truly is a revolutionary architecture for the PLL. The successful implementation of our PLL into AMD's microprocessor is a testament to the cooperation of the two companies and their combined skill and experience. We look forward to a long relationship with AMD." NurLogic's Industry Leading PLL Analog IP About AMD's Eighth-Generation Processor Family About AMD About NurLogic Design, Inc. Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121. ### NurLogic is a trademark of NurLogic Design, Inc. All other trademarks are the property of their respective owners.
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |