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Imagination launches world's first MCU-class CPU IP cores with hardware virtualizationMIPS Warrior M-class cores bring a new level of security and reliability to a wide range of entry-level smart embedded applications including IoT, wearables, automotive and more Embedded World Conference, Nuremburg, Germany – 24 February, 2014 – Imagination Technologies (IMG.L) is rolling out the world’s first microcontroller (MCU) class CPU intellectual property (IP) cores that incorporate hardware virtualization – bringing a new level of flexibility, security and reliability to entry-level applications. The low-power, compact, real-time MIPS M-class M51xx cores form the first group of entry-level MIPS Series5 Warrior CPUs, achieving the highest CoreMark/MHz scores for MCU-class processors. The M51xx cores are ideal for industrial control, Internet of Things (IoT), wearables, cloud computing, wireless communications, automotive, storage and other applications. Says Tony King-Smith, EVP marketing, Imagination: “With the MIPS Series5 M-class IP cores, we believe we’re bringing fresh thinking to the embedded world. For example, virtualization has long been considered a powerful technology for use in high-end applications such as servers. Imagination has seen the trends leading to the need for more advanced multi-context security and multiple execution domains right across the CPU spectrum, which is why we’re now rolling out virtualization across our entire range of MIPS Series5 CPUs, including the new entry-level M51xx family. “The exceptional performance and low power credentials of our latest M-class CPUs have already generated a lot of excitement with our key licensees and partners. And with advanced functionality such as virtualization, full FPUs and advanced DSP capabilities, complemented by mature tools both from ourselves and our ecosystem partners such as Mentor Graphics and Green Hills Software, we’re confident you’ll be hearing a lot more about MIPS embedded CPUs in the coolest and most disruptive chips and products.” The first available M-class cores are the M5100 and the M5150. The M5100 integrates a real-time execution unit and SRAM controller, and is optimized for low-cost, low-power microcontroller applications. The M5150 incorporates the same execution unit as the M5100, and adds a programmable L1 instruction and data cache controller, as well as memory management support for high-performance Linux and RTOS embedded system applications. Reflecting Imagination’s strength in embedded processing, previous-generation entry-level MIPS cores provide class-leading performance efficiency, and have been widely adopted across a broad array of applications. Imagination has already secured multiple licenses for the M51xx cores targeting embedded processing, automotive and beyond. As with other MIPS Series5 cores, the M-class cores implement the MIPS Release 5 architecture incorporating hardware virtualization. The M51xx cores are based on the same 5-stage pipeline architecture and leverage the high performance, comprehensive digital signal processing (DSP)/SIMD features of the previous generation MIPS microAptiv family of cores, along with the microMIPS Instruction Set Architecture (ISA) which provides up to 30% code size reduction over 32-bit only code. Virtualization: anticipating the needs of future With virtualization, multiple, unmodified, operating systems and applications can run independently and securely at the same time on a single, trusted platform. This delivers a range of benefits for system development, including:
Built-in prioritization mechanisms in the MIPS virtualization architecture, with support for up to seven secure/non-secure guests, enable it to optimally support real-time functionality. In space-constrained, low-power systems such as IoT or wearable devices, virtualization could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another guest, under RTOS control, can provide the multimedia capabilities of the system. For applications that demand an even higher level of security, the new M-class cores include tamper resistant features that provide countermeasures to unwanted access to the processor operating state. A secure debug feature increases the benefit by preventing external debug probes from accessing and interrogating the core internals. FPU: high-end performance, low-end size Tools: everything you need Availability About MIPS processors The CPU IP cores comprising the MIPS Warrior family come in three performance/feature classes:
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