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MPEG-4 Accelerator IP Core achieves ultra low power for multimedia communications silicon
MPEG-4 ACCELERATOR IP CORE ACHIEVES ULTRA LOW POWER FOR MULTIMEDIA COMMUNICATIONS SILICON
Belfast, Northern Ireland and San Jose, California (October 15, 2001) - Amphion Semiconductor Ltd., the leading provider of semiconductor intellectual-property (SIP) for multimedia, wireless and broadband communications, has further widened its technology leadership in digital video compression with the announcement today of the industry's most efficient MPEG-4 Video decoder core for System-on-a-Chip (SoC) integration. The Amphion CS6750 is a highly optimized application-specific accelerator core (comprising direct-mapped hardware and control software) for MPEG-4 Simple Profile (Level 1 - Level 3) Video decode at milliwatt levels of power consumption. Available as a standalone solution for integration into any embedded processor environment, the CS6750 enables MPEG-4 compliant streaming video clips, video e-mail, and multimedia messaging services for next-generation digital video products. Streaming Video solution for System-on-a-Chip The Amphion CS6750 MPEG-4 Video decoder is fully compliant with ISO 14496-2 Simple Profile, Level 1 to Level 3, with defined bit rates up to 384 kbits/sec. This core offers advanced features such as error resilience, integrated H.263 base-line, post-processing and color space conversion, yet requires less than 65K gates. As an illustration, at 15 frames/sec QCIF, the CS6750 requires only 12 MHz clocking, and provides full post-processing while using under 8 milliwatts in 180nm TSMC ASIC technology - and even less power in 130nm process technologies. Without post-processing, power consumption is reduced to about 4 milliwatts. Post-processing bonus The CS6750 accelerator core effectively liberates any embedded processor from the high computational load of decoding MPEG-4 Video. This enables the program developer to re-assign scarce processing power to the execution of value-added applications. The CS6750 comes complete with its own controller software, and has the added advantage of upgradability to handle future enhancements to the MPEG-4 standard. Early 2002, Amphion will introduce an equally impressive MPEG-4 Video codec. Looking further ahead, the Amphion architecture scales to handle higher bit rate video for studio quality applications such as digital cinema distribution. CTO McCanny added, "Direct-mapped DSP accelerator cores are clearly the wave of the future. Amphion technology has turned quite a few heads, and we are engaged today in multiple license opportunities." Applications beyond Wireless The CS6750 joins the Amphion range of video and imaging products which also includes a High-Definition MPEG-2 Video Decoder core for ASIC, an MP@ML MPEG-2 Video Decoder for FPGA, and Motion-JPEG cores for ASIC and FPGA. Technical datasheets and databooks for Amphion MPEG and JPEG products are available at www.amphion.com/video.html About Amphion Notes to Editors Press Contacts Ron Sailors, Amphion |
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