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Xilinx Ships Industry's First FPGA-Based Solution for SFI-4 and XSBI ApplicationsCompany provides fully scalable and flexible 644 MHz and 840 Mbps LVDS solutions for next generation data communication systems SAN JOSE, Calif., July 2, 2002- Xilinx, Inc. (NASDAQ:XLNX) today announced the availability of the 644MHz Single Data Rate (SDR) Low Voltage Differential Signaling (LVDS) solution for SerDes Framer Interface (SFI)-4 and 10 Gigabit Sixteen Bit Interface (XSBI) applications based on Xilinx® Virtex®-II and Virtex-II Pro Platform FPGAs. Designers of 10 Gigabit Ethernet and OC-192 SONET/SDH systems now have access to an off-the-shelf, flexible solution for addressing XSBI and SFI-4 interfacing requirements. Leveraging the powerful features of the Virtex-II FPGA series, such as digital clock managers (DCM), abundant Block RAM, and flexible and scalable LVDS I/Os, designers can now achieve the maximum performance required for SFI-4 and XSBI applications. For more information about this design or other Xilinx SystemIO solutions, visit www.xilinx.com/connectivity . "With the high-performance LVDS I/Os in the Virtex-II and Virtex-II Pro FPGA, we continue to provide ready-to-use, leading-edge interface solutions to our customers implementing SFI-4 and XSBI interface requirements," said Andy Debaets, senior director of Systems and Application Engineering at Xilinx. "The highly flexible and scalable SelectLVDS™ reference design provides a seamless interface to the third party framer and enables our customers to achieve maximum performance for their OC-192 SONET/SDH and 10 Gigabit Ethernet system designs." Xilinx SelectLVDS Reference Designs Xilinx also offers a fully scalable and flexible 840Mbps Double Data Rate (DDR) SelectLVDS reference design ( http://www.xilinx.com/xapp/xapp265.pdf ), allowing designers to implement the 16-bit LVDS channel in any location. The reference design is ideally suited for data traffic aggregation applications. To help designers implement applications such as high speed interfacing between a network processor unit (NPU) and a traffic manager, up to 7 groups of 16-bit transmitter/receiver blocks can be instantiated into a single Virtex-II Platform FPGA. The 840 Mbps reference design also provides multiple-channel options (4b, 16b or 20b) and is optimized for the Virtex-II Platform FPGA. License Price and Availability About the Xilinx Metro-Optical Networking Forum About Xilinx
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