IEEE Forms Two New Working Groups to Standardize Software and System-Level Energy Management and Power Modeling for System-on-Chip Devices

IEEE P2415™ and IEEE P2416™ will be created to augment existing standards for low-power design and verification methodologies for system-on-chip

PISCATAWAY, N.J. -- September 16, 2014 --IEEE, the world’s largest professional organization dedicated to advancing technology for humanity, today announced the formation of the IEEE P2415™ Unified Hardware Abstraction and Layer Working Group and IEEE P2416™ Power Modeling Meta-standard Working Group. Both new working groups will be drafting standards that are intended to support development of more powerful and economically affordable electronics.

“Mobile and wall-powered consumer devices continue to put stringent demand on battery performance, energy consumption and heat dissipation, which requires systems to implement many complex power-aware operational modes,” said Stan Krolikoski, chair of the IEEE Computer Society’s Design Automation Standards Committee (DASC), which is sponsoring both working groups. “Therefore, it is very important that the low-power design methodology for system-on-chip in use today continues to extend into the system and software domain covering complete electronic devices. I am very pleased that a year-long study group of more than 30 active participants has resulted in these two new standards projects.” This year-long low-power study group of industry experts was led by Yatin Trivedi, vice chair of DASC.

The proposed IEEE P2415 “Standard Project for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems” is intended to define the syntax and semantics for energy-oriented description of hardware, software and power management for complete electronic systems. It will enable specifying, modeling, verifying, designing, managing, testing and measuring the energy features of an electronic device, covering both the pre- and post-silicon design flow. On the hardware side, the description will address enumeration of on- and off-chip components, memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, energy and power attributes; on the software side, the description will address software activities and events, scenarios, external influences and operational constraints, and, on the power-management side, the description will address activity-dependent energy control. The new standard, once completed and approved, will be intended to be compatible with the current IEEE 1801™-2013 (UPF) standard¹ to support an integrated design flow. Additionally, the new standard would complement functional models in standard hardware description languages IEEE 1076™ (VHDL)², IEEE 1364™ (Verilog)³, IEEE 1800™ (SystemVerilog)⁴, and IEEE 1666™ (SystemC)⁵, by providing an abstraction of the design hierarchy and an abstraction of the design behavior with regard to power and energy usage.

“IEEE P2415 will provide the higher level of energy abstraction for the system-on-chip and the whole device and, therefore, will enable earlier (more abstract) modeling of power states using the IEEE 1801-2013 (UPF) standard,” said Dr. Vojin Zivojnovic, chair of the IEEE P2415 working group and CEO of Aggios, Inc. “Many software engineers and system architects will find this effort well-aligned with their need to communicate their low-power and energy requirements with the hardware engineers in an aligned fashion for holistic, quantifiable and reusable energy optimizations. I welcome them to participate in this industry-wide effort.”

The IEEE P2416 “Standard Project for Power Modeling to Enable System Level Analysis” is being created to propose a meta-standard focused on parameterization and abstraction, enabling system, software and hardware IP-centric power analysis and optimization. This standard, once completed and approved, will define the required concepts and semantics for the development of parameterized, accurate, efficient and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include process, voltage and temperature (PVT) independence, power and thermal management interface, workload and architecture parameterization. Resulting models will be suitable for use in both software-development and hardware-design flows, as well as in representing both pre-silicon estimated and post-silicon measured data.

“This standard will define the necessary requirements for the information content of parameterized, accurate, efficient and complete power models, to help guide development and usage of other related power, workload and functional modeling standards,” said Dr. Nagu Dhanwada, chair of the IEEE P2416 working group and technical lead for Power Tools and Methodology in IBM Systems and Technology Group. “Beyond defining the concepts and related standard requirements, the proposed specification will recommend the use of other relevant design-flow standards with the objective of enabling more complete and usable power-aware design flows. I invite experts from diverse power-modeling domains to contribute to this open and transparent process.”

IEEE P2416 will also benefit from technology contributions from Silicon Integration Initiative (Si2), which was an active participant in the year-long IEEE needs study. As Dr. Dhanwada is chair of the Si2 Low Power Coalition’s Model Working Group, efforts between the two organizations will be closely synchronized, ensuring that there is, eventually, one final repository for the resulting standard—namely, IEEE.

Both entity-based working groups are actively seeking participants for the development of these standards. For more information on the IEEE P2415 working group, please visit http://standards.ieee.org/develop/project/2415.html. For more information on the IEEE P2416 working group, please visit http://standards.ieee.org/develop/project/2416.html.

In standards development, the IEEE-SA offers the flexibility of either individual- or entity-based methods. In the individual method, participants are individual persons representing themselves, and each individual participant has one vote. Standards developed via the entity method are balloted using a “one-entity, one-vote” principle, allowing corporations, government agencies, academic institutions, nonprofits and industry associations to come together in collaboration to advance innovation.

IEEE 1801-2013, IEEE 1800-2012 and IEEE 1666-2011 are available at no charge via the IEEE GET Program, which grants the public free access to view and download certain current individual standards. To view and download these standards, please visit http://standards.ieee.org/about/get/.

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¹ IEEE 1801™-2013 “Standard for Design and Verification of Low-Power Integrated Circuits”

² IEEE 1076™-2008 “Standard VHDL Language Reference Manual”

³ IEEE 1364™-2005 “Standard for Verilog Hardware Description Language”

⁴ IEEE 1800™-2012 “Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language”

⁵ IEEE 1666™-2011 “Standard for Standard SystemC Language Reference Manual”