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Rambus Unveils On-chip Noise Monitor to Improve Quality and Reduce Time-to-Market of Complex SoCsCompact IP enables accurate characterization of power supply noise in mobile and server applications SUNNYVALE, Calif. – January 20, 2015 – Rambus Inc. (NASDAQ:RMBS) today announced the addition of an On-chip Noise Monitor to its suite of tools and IP cores. The Noise Monitor is a compact IP block that enables easy and precise noise measurements for both low-power mobile and high-performance server SoCs. Embedded on-chip, the noise monitor eliminates the need to use slow and often error-prone hand-probing techniques, improving the quality of silicon test results and speeding time-to-market. “As the system requirements for smartphones, tablets and servers continue to drive higher data rates and reduced power, designers are facing increasingly difficult challenges to accurately measure and characterize SoC power supply noise,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “The fast and accurate results delivered by the On-chip Noise Monitor provide designers a better understanding of the affects of noise and circuit performance and an increased confidence in the quality of IC design.” The Noise Monitor is an extremely small IP block that is integrated directly into the complex IC capable of measuring noise at frequencies as high a 6 gigahertz (GHz). This makes it ideal for high data rate applications, as well as those that use package-on-package and 2.5/3D packaging. When coupled with the Rambus LabStation™ Validation Platform, designers are able to precisely measure multiple aspects of power supply noise using only the LabStation Interface Module (LIM) and a personal computer. Rambus will be demonstrating the On-chip Noise Monitor along with its R+™ enhanced standard memory and serial link cores at the upcoming DesignCon 2015 conference in booth 835, January 28-29, 2015. About Rambus Inc.
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