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EEMBC Publishes Benchmark Scores for Toshiba’s TMPR4927 MIPS-Based 64-Bit RISC ProcessorEl Dorado Hills, Calif., Aug 5, 2002 - EEMBC, the Embedded Microprocessor Benchmark Consortium, today announced that that it has published certified benchmark scores for the TMPR4927, a 64-bit, MIPS-based RISC processor from Toshiba aimed at networking, printer, and other general-purpose applications. Tested against EEMBC's networking, consumer, office automation, and telecomm benchmark suites, the TMPR4927 achieved out-of-the-box consolidated scores of 3.8 Netmarks™, 14.2 Consumermarks™, 165 OAmarks™, and 2.9 Telemarks™. "This is Toshiba's third round of publications for EEMBC benchmarks. It is gratifying to see Toshiba among the industry leaders that are making validated performance information about its processors available to the public, and particularly since the TMPR4927 scores combine the architecture's efficient capabilities with that of the Green Hills compiler," said Markus Levy, EEMBC president. "Furthermore, the certification by the EEMBC Certification Labs helps ensure that these benchmark scores are credible and believable." "The EEMBC benchmark scores give customers confidence that the highly integrated TMPR4927 processor will meet and exceed performance requirements of their end product," said Farhad Mafie, vice president of TAEC's ASSP Business Unit. "Based on the Netmark consolidated score, the 200-MHz TMPR4927 achieved outstanding performance per MHz in the networking category compared to similar 32/64-bit processors that underwent the same rigorous testing. As a result, customers can benefit from faster packet transfers and even lower system costs," Farhad added. The TMPR4927 features a 5-stage pipeline that operates down to 1.5 V, 32K instruction and data caches, and a 100-MHz, 64-bit wide external memory bus. Its EEMBC performance is a result of an efficient core implementation, efficient memory access and cache implementation that supports a non-blocking cache feature. The device additionally incorporates a real-time, debug support unit. The core incorporates a memory management unit, hardware multiply accumulator and single/double precision floating-point unit. Peripherals include a PCI controller, direct memory access controller, and synchronous dynamic RAM memory controller, parallel input/output, AC-link, a UART and timer. "Green Hills Software is very pleased to have helped Toshiba achieve the outstanding EEMBC scores with our C compiler. By working together, Toshiba and Green Hills have optimized code generation that will benefit Toshiba's customers building products based on the TMPR4927," said Robert Redfield, director of Partner Programs, Green Hills Software, Inc. Detailed score reports for the TMPR4927 are available now from the Search Benchmark Scores area of the EEMBC web site ( www.eembc.org ) or direct from the following URLs: Networking Consumer Office Automation Telecomm About EEMBC EEMBC members include Altera, Aplix, ARC International, ARM, BOPS, Cadence, ChipWrights, DSP Group, Equator Technologies, Fujitsu Microelectronics, Green Hills Software, Hewlett-Packard, Hitachi America Ltd., IAR, Improv Systems, IBM Corporation, Infineon Technologies, Intel, LSI Logic, Metaware, Metrowerks, Microchip Technology, MIPS Technologies Inc., Mitsubishi Electric, Motorola, National Semiconductor, Nazomi Communications, NEC Electronics, Oki Semiconductor, Panasonic, Philips Semiconductors, PMC-Sierra, Precise, Red Hat, SandCraft, STMicroelectronics, Siroyan Ltd., StarCore, Sun Microsystems, SuperH, Symbian, Tao Group, Tensilica, Texas Instruments, 3DSP, Toshiba, TriMedia Technologies, Vulcan Machines, Wind River Systems, Xilinx, and Zucotto Wireless. EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. Netmark, Consumermark, OAmark, and Telemark are trademarks of the Embedded Microprocessor Benchmark Consortium. All other trademarks appearing herein are the property of their respective owners. |
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