Tensilica Unveils Xtensa V Architecture

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Xtensa Processor Reaches 350 MHz (Worst Case), Offers Extensive Support for Multiple, Unique Processors on a Single Chip

Santa Clara, Calif., August 26, 2002 – Tensilica, Inc., the leader in configurable and extensible processors, today announced the Xtensa V processor, its next-generation microprocessor core architecture that runs at 350 MHz (worst case), offers extensive support for multiple, unique processors in system-on-chip (SOC) designs and delivers superior performance on the industry-standard Embedded Microprocessor Benchmark Consortium (EEMBC) benchmarks.

"The enhancements to Xtensa V widen Tensilica's technology lead in the growing configurable and extensible processor category, and solidify our position among the world's leading suppliers of microprocessor intellectual property," said Chris Rowen, president and CEO of Tensilica.  "With over 100 designs in progress using our platform, customers are proving the performance, integration and time-to-market advantages of using the Xtensa processor in a Sea of Processors™ design style as a superior alternative to traditional SOC design styles."

Xtensa continues to be the only configurable and extensible processor with comprehensive and automatic software, modeling and EDA support. Changes made by the designer to extend the Xtensa processor hardware – adding instructions, registers, processor state and custom execution units - are immediately and automatically reflected in the entire software tool chain, significantly reducing design complexity and time-to-market.  By comparison, competitive architectures require the designer to manually adjust compilers, assemblers, debuggers, operating systems, instruction set simulators, co-verification models and EDA implementation scripts when user-defined hardware changes are made to the processor RTL.

Using the Tensilica Instruction Extension (TIE) language, designers can develop an unlimited variety of designer-defined instructions. Tensilica's processor generator technology creates a complete, correct-by-construction processor solution – hardware, software environment, modeling and EDA tools – in just over an hour. Each core can be optimized for virtually any application. This has made the Xtensa platform an attractive alternative to custom logic blocks, which were traditionally designed to accompany off-the-shelf, hard-wired processor cores in order to optimize the SOC for the target application.

Key Enhancements to the Xtensa Architecture

The Xtensa V core delivers all of the unique features of the previous flagship Xtensa IV processor and has been enhanced to include the following:

Extensive Support for Multiple, Unique Processors on a Single Chip: Tensilica continues to enhance its architecture to enable the further, rapid deployment of multiple, unique Xtensa cores on a single chip. For systems designed with shared memory / bus architectures, a new write-back cache option reduces system bus traffic and thus improves system performance. Tensilica also has added a processor ID register to the instruction-set architecture (ISA) that can identify each unique processor integrated on a SOC. This eases system software development and integration for natively parallel applications that deploy multiple copies of the same configuration of the Xtensa processor.

Interface Enhancements Increase Performance, Add Flexibility: Tensilica has enhanced the Xtensa Local Memory Interface (XLMI) to enable the attachment of multi-cycle devices with variable latency. Tensilica has also implemented an Incoming Request feature for the Xtensa processor interface (PIF) that enables Xtensa to simultaneously execute instructions and handle read/writes to the processor's local data memory from external agents such as DMA engines or other tightly coupled processors. These interface enhancements maximize the usable I/O bandwidth of the Xtensa V processor thereby enhancing the performance of Xtensa-based SOC devices. With configurable interface widths up to 128 bits the Xtensa processor delivers a peak I/O bandwidth of 45Gb/sec. Further, these enhancements facilitate better processor-to-processor and RTL-to-processor communication for added freedom and flexibility when embedding Xtensa cores.

TIE Language Improvements: Designers extend the Xtensa processor by describing new instructions, registers, state variables and complex execution units using the Tensilica Instruction Extension (TIE) language.  This single-source description is the specification used by Tensilica's processor generator toolset to produce the complete processor / tools / models.  The TIE language – a derivative of the popular Verilog language - has been enhanced in this release to support designer-defined conditional load and store instructions, which results in code that utilizes fewer branch instructions and thus delivers better overall performance. Tensilica also has increased designer productivity by expanding the range of optimized built-in function modules – such as a variety of adders and multipliers – used to describe designer-defined functional units, particularly in DSP applications.  These built-in TIE modules speed development of designer-defined TIE instructions and deliver maximum clock rate performance in the physical implementation..

Performance: Tensilica tuned both the design and tool flow to consistently achieve worst-case performance of 350 MHz in a 0.13-micron process for typical Xtensa V configurations.  Enhancements to the physical design flow, including automated scripting of Synopsys Physical Compiler-based design flow, are enabling Tensilica to deliver blazing-fast clock speeds that outperform other processor cores.

XCC Compiler Enhancements: With the Xtensa V processor release, Tensilica has optimized the Xtensa C-compiler (XCC) to deliver higher performance and reduce code size.  New features include cross-file inlining, interprocedural analysis and removal of unused functions, improved alias analysis and register scheduling, and numerous code generation improvements. The result is exceptional performance improvements that have been proven on multiple industry-standard benchmarks.

Industry-Standard Benchmarks Prove Xtensa's Performance Superiority

The enhancements made to Xtensa V, in particular to the XCC compiler, have enabled Tensilica to extend its lead in overall processor performance on two industry-standard benchmarks: EEMBC and Dhrystone.

In the EEMBC benchmark suite – an independently certified benchmark developed to measure the performance of processors in a variety of embedded applications – Tensilica posted the highest scores ever published for a processor core on the Consumer, Network, Telecom and Office Automation tests. In addition, Tensilica's Xtensa processor boasts the highest scores ever recorded on the Consumer test for any device – cores or full-chip CPUs. Both "Optimized" and "Out of the box" configurations of Xtensa were tested.  "Out of the box" tests measured the performance of cores using unmodified C-code, while "Optimized" tests measured the performance of Xtensa with modifications to the C code to utilize the TIE instruction extensions to optimize performance. No assembly coding was used in the EEMBC benchmarks, and no assembly coding is ever required to utilize the power of TIE extensions.

In each of the four EEMBC benchmark suites, Xtensa came out on top, outperforming cores from several high-profile processor companies including ARM, as well as companies offering processors based on the MIPS® RISC architecture. In some cases, the core was measured against full-chip, multi-million transistor, standalone microprocessor ICs that are as much as 100 times the size of the Xtensa core, proving the efficiency and integration enabled by the Xtensa architecture and the immense power of designer-defined extensions. Head to head against the ARM1020 the base Xtensa processor is 43 to 256 percent faster on out-of-the-box EEMBC benchmarks, while the optimized Xtensa core outperforms the ARM1020 8X to 33X.

Another universal yardstick for measuring processor performance is the Dhrystone benchmark (v2.1).  The Xtensa V 32-bit core outperforms processors from both ARM and MIPS on this benchmark, delivering 2.0 DMIPS/MHz with full optimization, and 1.2 DMIPS/MHz with no in-lining. By comparison, the ARM 1020E deliveres 1.7 and 1.2 DMIPS/Mhz, respectively. The recently introduced MIPS M4K 32-bit core delivers 1.35 DMIPS/MHz with full optimization, while the MIPS 5KCc 64-bit core delivers 1.4 DMIPS/Mhz, also with full optimization.

Pricing and Availability

The company's pricing structure is based on a licensing fee per processor instance plus royalties based upon volume of processors manufactured.  Each licensed processor instance can be targeted to any silicon foundry technology.  Licensing fees for a single processor configuration, including a complete, configured GNU-based software development toolchain, start at $350,000.  The Xtensa C compiler, Xtensa instruction set simulator, and Xtensa TIE compiler are priced separately. Customers can begin taking advantage of the new features of the Xtensa V processor in September of 2002.

About EEMBC

EEMBC, the Embedded Microprocessor Benchmark Consortium, develops and certifies real-world benchmarks and benchmark scores to help designers select the right embedded processors for their systems. Every processor submitted for EEMBC® benchmarking is tested for parameters representing different workloads and capabilities in communications, networking, consumer, office automation, automotive/industrial, embedded Java, and microcontroller-related applications. With members including leading semiconductor, intellectual property, and compiler companies, EEMBC establishes benchmark standards and provides certified benchmarking results through the EEMBC Certification Labs (ECL) in Texas and California.

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company has over 140 engineers engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Austin, Texas; Raleigh, NC; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

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Editors' Notes:

"Tensilica" and "Xtensa" are registered trademarks belonging to Tensilica Inc. EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium.  All other trademarks are the property of their respective holders.

Tensilica's announced licensees are Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co.Ltd., ONEX Communications, Olympus Optical, OptiX Networks, Osaka & Kyoto Universities, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.