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Arasan Chip Systems Announces the Industry's First UFS 2.1 IP SolutionsArasan, the leading provider of IP Cores for the JEDEC UFS and eMMC standards, announces Host Controller Total IP Solutions for the latest UFS standard 2.1 San Jose, CA October 8, 2015 -- Arasan announces availability of UFS 2.1 Host Controller IP core supporting a maximum throughput of 5.8 Gbps with M-PHY HS-G3 single lane, or 11.6 Gbps with M-PHY HS-Gear 3 2-lane operation, meeting the greater data transfer rates and lower power requirements of advanced mobile applications such as smartphone and tablets.
“The adoption of UFS for high capacity, high performance low power storage is accelerating as the ecosystem matures.”, said Arasan’s Director Marketing Sam Beal. Arasan’s UFS 2.1 digital controller IP has incorporated the MIPI UniProSM version 1.6 link layer with support for multi-lane operation and the optional Unified Memory Architecture (UMA) implementation. Arasan’s UFS 2.1 IP is available in both a Device Controller IP and Host Controller IP configurations, which incorporates the latest UFS Host Controller Interface (HCI) version 2.1. Arasan’s MIPI M-PHY® HS-G3 v3.1 IP is available in GDSII format for a variety of process technologies. In addition, Arasan’s Hardware Validation Platforms enable early validation of UFS 2.1 specification by emulating either a UFS 2.1 Host or Device systems at the interface protocol level. Arasan’s UFS Host, Device and MPHY IP’s have been licensed and are in production with leading NAND Flash memory vendors and Application Processor companies. UFS Compliance and Production Testers from leading vendors also use Arasan’s UFS IP in combination with it’s MPHY operating at Gear 3 speeds. Arasan’s UFS solutions can be found in some of the leading edge smartphones available in the market today. Availability About Arasan About JEDEC About the MIPI Alliance
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