Synopsys’ VERA speeds Verification of SONET/SDH Chip at NEC

VERA Chosen as the Preferred Testbench Tool for SONET/SDH Projects in NEC Electron Devices

MOUNTAIN VIEW, Calif., September 3, 2002 -- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today announced that NEC Electron Devices (NEC), a leading provider of Internet solutions, has successfully verified its latest SONET/SDH framer physical layer chip with Synopsys' VERA® testbench automation tool. VERA's advanced features such as its easy-to-learn, intuitive OpenVera™ hardware verification language, allowed NEC engineers to verify their design quickly and meet demanding schedules with a high quality, reusable verification environment.

The NEC SONET/SDH framer (uPD98413, http://www.ic.nec.co.jp/comm/en) incorporates four, 622 megabit per second, synchronous optical network/synchronous digital hierarchy channels on a single chip, making it ideal for high-end WAN applications. Verifying the chip was complex, which necessitated the creation of a random stimulus generator. This shortened the verification time and achieved the desired coverage.

The ability to monitor packet flow and track device coverage is another verification essential. VERA's rich feature set, which includes constraint based random generation, automated self-checking and functional coverage, made it possible for NEC to meet these requirements. Using VERA's constraint-based stimulus generator and concise modeling constructs shortened the time required to develop the testcases and models. Additionally, the integration with VCS™ Coverage Metrics technology permitted the tracking of simulation coverage to monitor progress of the verification flow. The success with the SONET/SDH design has proven VERA as an effective testbench automation tool.

"The success achieved with VERA at NEC is made possible by the tightly integrated solution of the Synopsys VERA testbench tool and its industry-leading VCS Verilog simulator. This solution provides NEC a high performance, constraint-driven testbench automation tool," said Swami Venkat, director of marketing of testbench and formal analysis for the Verification Technology Group at Synopsys. "NEC's WAN designs are extremely complex and require a powerful, yet easy-to-use tool to verify them. NEC was able to thoroughly verify their designs using the powerful capabilities built into this tool."

VERA Raises Verification Quality
VERA provides full support for automatic generation of stimulus, including the ability to generate directed, random and constrained random tests. The user can specify valid ranges for complex data types and constraints for protocols to focus on difficult corner cases. Additionally, VERA can take user-defined production rules and automatically generate a continuous stream of legal random sequences for commands or packets. With these capabilities, VERA can be used to generate many different combinations of legal stimulus to find design errors early in the verification cycle and raise the overall quality of the verification environment.

VERA allows NEC to streamline the verification environment while providing a highly effective verification solution. A verification environment created using VERA, can be reused due to built-in support for object-oriented programming. Prior to using VERA on testbench projects, NEC found that it was difficult to establish a common coding style and methodology. With VERA, bus-functional models, transaction generators, functional coverage objects and other elements of the verification infrastructure can be easily reused in other projects and shared among different locations. The concise nature of the OpenVera language and its support for reentrancy has also reduced the overall size of the testbench, easing maintenance issues.

Complete Functional Verification Solution
Synopsys offers a complete line of integrated functional verification solutions aimed at achieving the highest functional coverage in the shortest amount of time for complex IC designs. These solutions include Synopsys' VCS Verilog simulator, Scirocco™ VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, CoCentric® System Studio for SystemC simulation, VERA testbench automation tool, DesignWare® verification IP, LEDA® programmable HDL checker, NanoSim™ circuit simulation and Formality® equivalence checker.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, Calif., creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems-on-a-chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com/.

Synopsys, VERA, DesignWare, LEDA, and Formality are registered trademarks of Synopsys Inc. VCS and OpenVera are trademarks of Synopsys Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.