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CAN FD Bus Controller IP Core Gains Time-Triggered TTCAN CapabilityAvailable from CAST, Inc. this fully-featured soft CAN FD core supports all relevant specs, has Verification IP available, and will undergo its second Plug Fest in April Nuremberg — Embedded World — February 23, 2016 — Semiconductor intellectual property provider CAST, Inc. today introduced standard support for the new Time-Triggered communication on CAN (TTCAN) protocol in the CAN Bus Controller IP Core it offers. This CAN-CTRL CAN 2.0 & FD Controller Core, sourced from partner Fraunhofer IPMS, is among the few ASIC RTL and FPGA netlist cores to support TTCAN, the Flexible Data-Rate CAN FD protocol, and all popular CAN bus specifications:
This CAN core was the first soft core to undergo rigorous testing at the CAN Open Plug Fest (in March 2015), and is scheduled for a second round at Detroit and Nuremberg Plug Fests in April and June respectively. Subsystem boards with the CAN-CTRL core and transceivers from ON Semiconductor and Microchip will be used in these strenuous evaluations. Design verification for CAN-CTRL Core customers is facilitated through a partnership with verification IP expert Avery Design Systems. Developed independently but cooperatively, the Avery CAN 2.0 and FD VIP works “out of the box” with the core to provide smooth design and verification. A ready-to-run reference design board and other development aids are also available from CAST to further shorten the time to market for CAN FD based systems. Visitors to Embedded World and DVCon (San Jose) are welcome to stop by the CAST booth for more information. CAST, Inc. is a twenty-year-old developer, integrator, and aggregator of IP cores for ASICs and FPGAs. The company offers some of the best available choices for low-power, high-value IP, including 8051s and BA2x 32-bit Processors; video, image, and data compression; peripherals, interconnects and other functions needed for complete system designs. Visit www.cast-inc.com.
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