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Barcelona Design to Offer Analog IP for 90 nm Technology NodeUpdate: Barcelona has been bought by Synopsys Newark, Calif., September 24, 2002 -- Barcelona Design Inc., the leading provider of synthesizable full-custom analog intellectual property (IP), today announced its plan to develop products at the 90 nm technology node. Taiwan Semiconductor Manufacturing Company (TSMC) – the world's largest semiconductor foundry – is expected to share technology information with Barcelona to support the development of analog intellectual property (IP) engines based on TSMC's Nexsys™ 90 nm process technology.
"The 90 nm process node is designed for System-on-Chip (SoC) products, which require analog IP customized to meet specific application requirements", said Peter Santos, VP of Marketing and Business Development at Barcelona Design. "Barcelona's revolutionary synthesizable analog IP offers the flexibility and performance SoC designers need to innovate and accelerate time to market."
Barcelona said that it would provide synthesizable analog or mixed signal components for analog functions such as phase-locked loops and data converters designed to meet the requirements of SoCs targeted at the computing, communication and consumer segments. Barcelona intends to launch its first 90 nm product in 1H03.
"Barcelona's initiative to develop IP targeted to TSMC's Nexsys 90 nm process allows us to cover a large application space very early in the lifecycle of this process technology. Barcelona's IP is expected to foster innovation and improve time-to-market for leading-edge SoC products," said Genda Hu, VP of Corporate Marketing at TSMC.
TSMC works extensively with industry-leading third-party IP providers to create the foundry industry's most comprehensive process-specific IP portfolio at technology nodes ranging from 0.25 micron to 90 nanometers. These process-proven cores provide designers with increased assurance of right-the-first-time silicon while reducing overall engineering and out-of-pocket expenses. Without this service, many design engineers would have to develop their own IP or purchase custom cores, all of which considerably delays time-to-volume.
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