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Xilinx Ships World's First PowerPC with RapidIO InterfaceXilinx accelerate's industry-wide adoption of RapidIO with Virtex II Pro - world's fastest FPGA
COMMUNICATION DESIGN CONFERENCE, SAN JOSE, Calif., September 23, 2002 -Xilinx, Inc. (Nasdaq:XLNX) today announced the immediate availability of its Virtex-II Pro™ device containing the world's first PowerPC processor with RapidIO™ interface. System architects in need of an overall system performance boost can now leverage the tightly integrated IBM PowerPC processor and RapidIO interface to implement high performance, low latency applications such as network control planes, DSP traffic aggregation and enterprise storage channel processing. Developed in collaboration with IBM, the complete solution leverages the embedded PowerPC processors and proven SelectI/O™-Ultra of the Xilinx Virtex-II Pro programmable platform. For complete information about the Virtex II Pro device with RapidIO interface, visit www.xilinx.com/connectivity.
Today's news underscores the benefits of the technology relationship between Xilinx and IBM in bringing innovative and flexible new solutions to market. The Xilinx Virtex-II Pro FPGAs are the result of a collaborative design effort between the two companies to deliver a new platform for use in communications, storage, and consumer applications.
"We're working with Xilinx to provide our embedded PowerPC customers with new development options for their products," said Scottie Ginn, vice president of standard products for the IBM Microelectronics Division. "We believe Xilinx's integration of PowerPC, Virtex-II Pro, and RapidIO technologies represents a unique and powerful combination."
"Xilinx is pleased to be collaborating with our key partner IBM to accelerate the industry-wide adoption of the RapidIO interface," said Rich Sevcik, senior vice president of FPGA Products at Xilinx. "Starting with our introduction of the first RapidIO core in May, 2001, Xilinx continues to offer the industry's broadest family of RapidIO building blocks to provide system architects with greater IO and processing performance for building scalable next generation programmable systems."
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