Amazing improvement of power and density for RFID chips with standard cell libraries at 180 nm from Dolphin Integration

Grenoble, France - September 26, 2016 -- For RFID Tags, dynamic power is a critical factor as the capability for lower power translates immediately into a wider range of detection (RFID tag read range) and/or a highest identification rate in the same range.

The main degree of freedom to improve power and area of RFID tag is located in the digital block.

The SESAME eLC standard cell library enables up to 50% savings of dynamic power when compared to any other logic library available at 180 nm. Such a comparison must be based on the Motu uta v6.0 benchmark with its Tsunami testbench (see results below), providing a quick and simple way to the expected improvement of overall performances of RFID tags.

Figure 1: SESAME eLC versus a free library - Dynamic power comparison at TSMC 180 nm G

Post-synthesis results, based on Motu-Uta V6 RTL benchmark – worst case conditions (SS 1.62 V 125°C )

Conversely, if area saving is more critical, SESAME uHD library represents the best trade-off between high density and low power consumption. This library, which proudly claims to be the densest library available at 180nm, enables up to 25% area reduction (see figure below). For RFID chip dominated by its digital area, the overall area saving represents the decisive incentive to opt for SESAME uHD library.

Figure 2: SESAME uHD versus free library - Silicon area comparison at TSMC 180 nm G

Post-synthesis results, based on Motu-Uta V6 RTL benchmark – worst case conditions (SS 1.62 V 125°C )

I want more information about these standard cell libraries at 180 nm

About Dolphin Integration

Dolphin Integration contributes to "enabling low-power Systems-on-Chip" for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at low-power consumption.

"Foundation IPs" includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. "Fabric IPs" of voltage regulators, Power Island Construction Kit and their control network MAESTRO enable to safely implement low-power SoCs with the smallest silicon area. They also star the "Feature IP": from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.

Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make DOLPHIN Integration a genuine one-stop shop addressing all customers' needs for specific requests.

It is not just one more supplier of Technology, but the provider of the DOLPHIN Integration know-how!