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CoWare and Denali Team to Speed Memory System Design and VerificationIntegration of Denali MMAV and CoWare N2C products enables advanced memory system simulation and verification for system-on-chip designs Palo Alto and San Jose, Calif.,---October 7, 2002 CoWare™ and Denali Software Inc. today jointly announced a solution that provides designers with an integrated platform for simulating memory and optimizing memory system performance for system-on-chip (SoC) designs. Denali's MMAV verification intellectual property (IP) software is now integrated with the CoWare N2C® system-level design environment.
By using Denali MMAV memory models in the CoWare N2C methodology, designers have access to robust simulation models for virtually any commercial memory device.
During simulation, the models provide valuable performance metrics for the memory system, and automatically test for potential design bugs at the memory interface. The C-based models from Denali are integrated directly with CoWare N2C, providing a seamless simulation and verification environment for advanced SoC development.
"The need to shorten the design cycle and increase system performance is crucial to success in digital consumer electronics market," said Seiji Yamaguchi, Group Manager of EDA, Matsushita Electric Industrial, Semiconductor Company. "We use N2C to verify chips for digital consumer electronics products. The integration with Denali's MMAV enabled us to analyze the performance of our memory system without leaving the N2C environment. This gave us a tremendous advantage in evaluating the impact of various memory system configurations on overall system performance, and we were able to use the same memory models at a later stage during functional verification."
"Memory can make or break system performance in today's complex SoC designs," says David Lin, Denali's vice president of applications engineering. "The integrated solution from CoWare and Denali gives designers the ability to optimize the impact of memory decisions at the bottom line."
"Increasing bandwidth requirements from new applications, and lack of specialized tools for memory simulation and analysis has made the interface to memory one of the most critical bottlenecks in system design," adds Pete Hardee, director of product marketing at CoWare. "Designers using CoWare and Denali will have a tremendous advantage because they can quickly analyze the effects of various memory architectures on overall chip performance."
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