SilabTech Announces Release of Trace Port PHY (HSSTP) for debug of Multiple Cores designs

Update: Synopsys Acquires Silicon and Beyond Private Limited to Expand High-Speed SerDes IP Portfolio (March 21, 2018)

Bengaluru (India) – Oct 25th, 2016 –SilabTech, a leading supplier of high speed serial interface intellectual property designs (IP cores) announced today the release of its High Speed Serial Trace Port (HSSTP) PHY. This IP Core is silicon proven on TSMC 28HPC and was successfully delivered to a Tier-1 global semiconductor company. The IP is tested on silicon to comply with ARM HSSTP Standard and has passed interoperability tests with GreenHills and Arium Emulators.

SilabTech HSSTP PHY is designed to enable probing of high speed on-chip signals like embedded processors and memory buses across multiple clock and power domains. This Trace Port IP provides access at a speed that matches advance cores operational frequencies and enable SOC debugging and problem solving on real time basis. SilabTech HSSTP PHY is available in 28nm and 40nm technologies, at datarate of upto 12.5Gbps per lane and supporting lane configuration of 1 to 6 lanes to be associated with one Link Layer Controller. HSSTP is an ARM standard based on AURORA Link Layer protocol and when used with a set of tools from ARM Eco-System enables efficient data collection, analysis and debug.

“We have released this product in a record time while being able to run rigorous pre-silicon verification and to complete silicon characterization across extreme operating conditions” said Gopal Krishna Nayak, SilabTech VP of Engineering, and added “we are happy to be part of the ARM Eco-System community and contribute our high speed PHY to enable shorter time to market and reduce development cost for SOC designers”.

SilabTech will be presenting its HSSTP and other products this week at ARM Tech Conference in Santa-Clara, CA.

About SilabTech

SilabTech is a semiconductor IP provider that aims to bring innovative design approaches to the ever increasing challenge of chip-to-chip and backplane high speed connectivity. The company has a track record of building high speed SERDES IP cores and in integrating them at chip top level. SilabTech specializes in low power processes and advance nodes such as 28 & 40 nm. Among the company customers are top multinational semiconductors and fabless IC companies, system companies and ASIC design houses.

For more details on SilabTech please visit www.silabtech.com