Flex Logix High-Performance Embedded FPGA IP Core Now Available for TSMC 16FF+ and 16FFC

Reconfigurable embedded FPGA to transform the design of data center, networking and base station chips

MOUNTAIN VIEW, Calif., December 13, 2016 – Flex Logix Technologies, Inc., the leading developer of embedded FPGA IP cores and software, today announced it has completed design of a high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions. Expected to be fully validated in silicon in early 2017, the EFLX-100 embedded FPGA IP core for TSMC 16FF+ and 16FFC will enable customers to design their next-generation networking, base station and data center chips with reconfigurable RTL that can be quickly, easily and cost-effectively updated or changed at any time after fabrication, even in-system.

“Configurable-cloud data centers will change the world with their ability to reprogram a data center’s hardware protocols: networking, storage and security,” said Geoff Tate, CEO and co-founder of Flex Logix. “High performance embedded FPGA enables this ability in chips cost effectively and at high performance.”

The EFLX-100 embedded FPGA core in TSMC 16FF+ and 16FFC has an architecture optimized for high speed control logic where hundreds of signals can be processed at speeds around 1GHz with single stage RTL logic, producing dozens of control signals. The EFLX-100 can be “arrayed” to build high speed control logic blocks from ~100 LUTs to ~3000 LUTs. The 16nm version of EFLX-100 has two architectural changes and physical design optimatizations from the 40nm version:

• 224 inputs and 224 outputs: increased I/O enables wider control signal paths to be processed
• 6-input LUTs (which can also be dual 5-input LUTs): enables more processing to be done in a single stage for higher logic density and higher performance
• The power bus has been designed to be very robust to handle high switching activity at 1GHz+ at worst case PVT conditions
• The core operates over the full range of voltages
• The core requires only 5 routing layers of metal and is compatible with almost all metal stack ups
• An EFLX-100 IP core in TSMC 16FF+/FFC has an area of 0.05mm²

Flex Logix has already begun design of the larger EFLX-2.5K embedded FPGA IP cores in TSMC 16FFC: both the all-logic and DSP versions, which are interchangeable to build arrays over 100K LUTs. These will be available in early 2017 and will be validated in silicon. A TSMC 16FF+ version will also be available. The EFLX-2.5K enables large, fast array that can be used to implement accelerators for wireless base stations, networking and data center processor acceleration functions.

The design kit for the Customer’s requested EFLX Array includes GDS-II, LIB, LEF, Verilog model, CDL/Spice netlist, Test Vectors, Validation report, detailed Datasheet, Integration Guidelines & the EFLX Compiler.

EFLX Compiler for TSMC 16FF+ and 16FFC

The software for programming and checking timing performance is available now for TSMC 16FF+ EFLX-100 arrays. Flex Logix offers evaluation licenses at no cost so designers can check RTL performance and architecture ideas.

Validation Silicon in Fab

Flex Logix proves out all of its IP cores in silicon for each major process node to ensure low risk of integration, even though its IP is all digital and compatible with logic DRC rules and the IP is simulated under worst case conditions: maximum frequency, high utilization and RTL with very high toggle rates to check for worst case static and dynamic IR drops. Validation verifies in silicon that the recommended power grid architecture enables full speed operation at full utilization with high toggle rates under worst case conditions. The company checks enough array combinations to be sure that the inter-core array-interconnect is functional on all sides thus ensuring array reliability.

Flex Logix uses an on-chip PLL to test on-chip at frequencies of 1GHz+ and above to confirm all functional and performance operation over the full temperature and voltage range. Each EFLX array interconnects with external I/O for test and with on-chip SRAM for high speed pattern testing. Each array has a process, voltage and temperature monitor to ensure precise control over testing at worst case conditions. Power domains are dedicated to each EFLX array and separately for SRAM and I/O and PLL so voltage range can be measured precisely for each IP. Once validation is complete, a detailed validation report will be available under NDA to interested customers.

The validation chip for the EFLX-100 IP cores in TSMC 16FF+/FFC will soon be in fabrication, and expected to complete validation in early 2017.

About Flex Logix

Flex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores and software. Flex Logix is the leader in embedded FPGA with the widest offering on the most process nodes, including the 3 highest volume process nodes: TSMC 40ULP/LP, TSMC 28HPM/HPC and TSMC 16FF+/FFC. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers’ hardware. Flex Logix is backed by leading venture firms Lux Capital and Eclipse Ventures and headquartered in Mountain View, California, with additional sales rep offices in China, Europe, Israel, Taiwan and Texas. More information can be obtained at http://www.flex-logix.com or follow on Twitter at @efpga.