Lattice Semiconductor and Velio Communications Demonstrate Interoperability in 180Gb/s STS-1 Grooming Switch Solution

Lattice's New ORSO82G5 Backplane FPSC and Velio's Zeus Switch Device Interoperable Across 56" of FR-4 

HILLSBORO, Ore. November 4, 2002 - Lattice Semiconductor (Nasdaq:LSCC), the leading supplier of integrated programmable logic and SERDES solutions, and Velio Communications, Inc., a leading developer of high-speed communications semiconductors, today announced they have demonstrated complete interoperability between Velio's VC2002 and Lattice's ORSO82G5 programmable backplane field programmable system chip (FPSC). The solution combines a Velio ZeusTM switch fabric for switching SONET streams at the STS1 level and Lattice's new ORSO82G5 FPSC for interfacing to SONET-based backplanes.

"Lattice is committed to demonstrating interoperability with leading communications IC vendors like Velio. We feel that these tests are assurances to customers that our system-level solutions will provide significant time-to-market advantages," commented Stan Kopec, vice president of marketing at Lattice Semiconductor. "We're eliminating the problematic and time-consuming interconnect debugging that can slow the delivery of high-speed system solutions," Kopec added.

"The interoperability test between the Lattice Semiconductor FPSC ORSO82G5 and the Velio VC2002 STS1 Grooming Switch family has been very successful. It proves the reliable and stable functionality of customer architectures using Velio and Lattice parts up to 56" of FR4 signal trace length," commented Bill Woodruff, vice president of marketing at Velio Communications. "Lattice's ORSO82G5 FPSC technology allows our Zeus grooming switch to seamlessly interface with existing and emerging SONET line cards, thus preserving the carrier's enormous investment made in SONET-based systems."

The Zeus switch (VC2002) is a 180Gb/s throughput, 72x72 STS-48/STM-16 SONET/SDH Grooming Switch, with STS-1/AU-3 granularity. For STS-192 traffic, the Zeus switch is an 18x18 Grooming Switch (with 1:4 de-interleaving). It allows each STS-1 component of each input stream to be directed to an arbitrary STS-1 slot in an arbitrary output stream. In effect, it is a 3456 x 3456 STS-1 switch.

The Lattice ORSO82G5 FPSC offers a clockless high-speed serial interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORSO82G5 supports higher system performance, easier-to-design clock domains in a multi-board system, and fewer signals on the backplane. The ORSO82G5 supports SONET data scrambling & descrambling, streamlined SONET framing, transport overhead handling, cell insertion and extraction, idle cell insertion/deletion, plus the programmable logic to provide high-speed data path functionality.

The SERDES technology in the VC2002 is based on Velio's industry-leading GigaCore serial I/O technology, which uses transmit pre-emphasis and receive equalization to improve transmission signal integrity. The VC2002 interfaces with the ORSO82G5 over dual sets of four CML streams at 2.488 Gbits/s. Its dual banks can be switched in a hitless fashion for error-free data protection.

The Lattice SERDES is the same technology employed in its ORT82G5 FPSC, a backplane transceiver featuring 8b/10b coding for use in high-speed Ethernet applications. The SERDES macrocell on the ORSO82G5 features programmable data rates from 1.0-2.7 Gbits/sec, and includes transmit pre-emphasis (programmable) for improved receive data eye opening. Test results confirm a high level of margin in the data eye opening at the receiving Lattice device. A technical note discussing the interoperability results can be found on the Lattice web site at http://www.latticesemi.com.

Additional ORSO82G5 Technical Information

• High-speed SERDES programmable serial data rates of 1.0 Gbits/s to 2.7 Gbits/s

• Provides a 10 Gbits/s backplane interface to switch fabric with protection

• Transmit pre-emphasis (programmable) for improved receive data eye opening

• No knowledge of SONET/SDH needed in generic applications. Simply supply data (125 MHz-168.75 MHz clock) and an optional frame pulse

• Eight-channel HSI function provides 2.7 Gbits/s serial user data interface per channel for a total chip bandwidth of >20 Gbits/s (full duplex)

• FIFOs optionally align incoming data across groups of two, four, or eight channels

• In-band management through transport overhead insertion and extraction. Options to insert SONET TOH bytes or have them automatically inserted with Default values

• Programmable enable of SONET scrambler/ descrambler

• Two 4K x 36 dual-port RAMs with access to the programmable logic

• Optional bypass of SONET frames for raw data interface to the FPGA logic

• Optional Cell Mode available that uses SONET for physical layer and cells inserted as payload

• Multiple fixed-length cell payload sizes available (64, 68, 72 or 80 bytes)

• Cell generation and insertion into payload on Tx cell extraction and error checking on Rx

• Automatic idle cell generation and deletion for rate matching

• Cell striping available in quad 2-link or single 8-link modes

• High Performance ORCA® Series 4 FPGA Gates Internal performance of > 250 MHz

• Over 400k usable system gates in FPGA section

• 1.5 V operation (30% less power than 1.8 V operation)

Comprehensive I/O selections including LVTTL, LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT, DDR, LVDS, bused-LVDS, and LVPECL Additional Velio VC2002 Technical Information

• 72x72 STS-48/STS-48c (2.48 Gb/s) or 18x18 STS-192/STS-192c (9.95 Gb/s de-multiplexed 1:4) Cross-Connect for high bandwidth, intelligent switching capability:180 Gb/s In -- 180 Gb/s Out with STS-1 level grooming capability

• Low 11W-20W power consumption

• Cross-Connect switching at STS-1 granularity (3456 x 3456), non-blocking for unicast, dualcast and multicast traffic

• SONET/SDH Input Processing per channel

• 2.5 GHz on-chip Clock Recovery/Demultiplexer

• Frame detection, byte monitoring

• SONET/SDH Output Processing per channel

• 2.5 GHz On-Chip Clock Generation/Multiplexer

• Single Byte Insertion within a frame for diagnostics

• CML high-speed serial I/O with programmable output, can be tailored to specific system conditions on a per-channel basis

• Adjustable pre-emphasis on serial outputs reduces inter-symbol-interference

• Optional receiver equalization on serial inputs reduces inter-symbol-interference

• 37.5 mm x 37.5 mm BGA thermally enhanced package

About Velio Communications
Velio is a leading provider of high bandwidth/low power semiconductors that solve the intra-system communications challenges faced in the architecture of next generation communications and storage platforms. Founded in 1998, Velio has achieved more than 50 design wins with Tier One and Tier Two customers in telecom, datacom and storage markets and is shipping for revenue its Storage SerDes, Data SerDes, SONET/SDH SerDes and STS-1 Grooming Switch. Venture funded by leading firms such as Sequoia Capital, Redpoint Ventures and Capital Research Group, Velio is headquartered in Milpitas, Calif., and has design centers in Lowell, Massachusetts, Chapel Hill, North Carolina and Princeton, New Jersey. For more information on Velio Communications, visit www.velio.com or contact the company at (408) 474-0700.

About Lattice Semiconductor
Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISPTM programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System Chip (FPSC) devices. Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise and the most advanced SERDES technology.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503/268-8000, FAX 503/268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

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