Extensive Rule Set Enforces IP Reuse Guidelines for ASIC and SoC Designs
SAN JOSE, CA. - November 5, 2002 - Atrenta™ Inc., the Predictive Analysis Company, announced that its award-wining SpyGlass® Predictive Analyzer now includes the new STARC (Semiconductor Technology Academic Research Center) policy, an extensive set of analyses based on the widely used HDL Design Style Guide by HD Lab. The HDL Design Style Guide is a book of standards for design guidance and design rules, developed jointly by HD Lab and STARC, a consortium of eleven major Japanese semiconductor companies that promotes a design standard for IP trade and reuse. Atrenta partnered with HD Lab to automate these guidelines as SpyGlass rules that enable ASIC and SoC designers to perform in-depth structural analysis on Verilog and VHDL Register Transfer Level (RTL) descriptions and ensure compliance with best practices and IP reuse guidelines based on the STARC rules.
"The STARC policy represents the collective knowledge of eleven major Japanese corporations that worked together to produce best practices guidelines for designing reusable IPs and complex SoCs in a very efficient manner," stated Dr. Toyoki Takemoto, president and CEO of STARC. "Several years of research proven by practical results were involved in developing these design guidelines - it is one of the most comprehensive collections of best design practices."
"The HDL Design Style Guide is packed with STARC's proven techniques, know-how and design rules, which lead to successful SoC projects, design re-use initiatives and IP development," said Mr. Yoshifumi Nagano, president of HD Lab. "Atrenta has developed a comprehensive set of analyses based on the Guide to help users quickly identify RTL style that should be followed to ensure compliance and best practices."
"To successfully complete large design projects, design re-use and use of IP provided by 3rd parties is a must," said Mr. Tadahiko Nakamura, vice president and general manager, IP Development Department, STARC.
"The STARC guideline is an important milestone in standardizing on the best design practice for IP reuse. Atrenta's STARC policy for SpyGlass is one of the most versatile and easy to use analysis tool for RTL design engineers who want to benefit from the STARC guidelines."
"The STARC guidelines are the 'the best of the best' IP reuse guidelines assembled in one place," said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. "Atrenta's SpyGlass leverages this knowledge and expertise and brings the benefits of Japan's best practices to the design community worldwide. The STARC policy is a major step in Atrenta's progress towards bringing the best design techniques in the industry to its customers."
About STARC Policy for SpyGlass
The STARC Policy for SpyGlass performs in-depth structural analysis on Verilog and VHDL RTL to ensure IP reuse guidelines are followed for ASIC and SoC designs, reducing iterations and rework and speeding new designs through IP portability. To ensure compliance and best practices according to the STARC guidelines, SpyGlass leverages STARC design expertise to quickly identify RTL constructs that should be changed. It includes a comprehensive set of analyses focused on such areas as synchronous design, initial reset conditions, hierarchical design, asynchronous circuits, clocks, and much more. SpyGlass offers the STARC guidelines as rules for both Verilog and VHDL analysis.
Availability
STARC is now available as part of SpyGlass Predictive Analyzer at no additional charge. It supports both Verilog and VHDL.
About Atrenta
Atrenta offers a new approach in accelerating the design of complex SoCs, ASICs, and FPGAs through predictive analysis. Its award-winning SpyGlass software is the first tool that performs detailed structural analysis on register-transfer-level Verilog and VHDL code in order to check for complex problems, which include coding styles, RTL-handoff, design re-use, clock/reset requirements, DFT and much more. Its breakthrough and innovative "look-ahead" capability incorporates a fast-synthesis engine, logic evaluator, and testability technologies. Atrenta has over fifty customers, including Agere, Agilent, Apple, ARM, Canon, Compaq, Fujitsu, Hitachi, Motorola, National Semiconductor, Nortel, Olympus, and Toshiba, who are using SpyGlass to achieve shorter overall design cycles, increased design productivity and lower costs. Atrenta is headquartered in San Jose, California, with European offices in England and France, a research and development center in India, and sales and support distributors in India, Israel, Japan, Korea, Singapore, and Taiwan. For further information, visit the Atrenta website at http://www.atrenta.com or call 408-453-3333.
