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SuperH Announces VSI Compliance for SuperHyway Interconnect and Presents at 'IP Based SoC Design WorkshopSan Jose, California and Bristol, UK - 30 October 2002 SuperH, Inc., the leading supplier of multimedia RISC CPU cores has this week announced that its high speed SoC interconnect, the SuperHyway, is VSIA 2.1 Compliantâ„¢.
The strategy of SuperH, Inc. is to deliver a package of IP and tools that enables SoC developers to integrate SuperH CPU cores easily in to their designs. A key part of this plan is the delivery of design kits and technology such as the VSI compliant SuperHyway interconnect which is licensed to customers along with the SuperH CPU core. This package also incorporates sophisticated on-chip debugging facilities for run-time control and tracing during the development and debugging of SoC devices.
For highly integrated multimedia SoC devices the performance of the on-chip interconnect is one of the key factors in delivering system performance. The SuperHyway is an advanced interconnect fabric that can be optimised for each specific SoC device. A toolkit enables users to define the number of ports, latency and bandwidth requirements of the interconnect. Licensees of the SuperH CPU core and SuperHyway interconnect can easily add peripherals designed for different bus and interconnect standards allowing them to mix and match IP for a specific application.
SuperHyway VSIA compliance is a major benefit in enabling customers to easily develop SuperH based SoC devices with the growing library of VSI compliant IP in the marketplace. Rick Chapman, SuperH vice president of marketing and sales said: ''By becoming a member of VSI and being fully compliant with their standards, SuperH licensees will benefit from the interoperability and shared engineering that has been completed within the VSI organization. This will ultimately enable our customers to reduce their time to market and to access more advanced technology in a shorter period and at a more cost effective price.''
At the 'IP based SoC Design Workshop' in Grenoble, France on 30/31 October, Rob Deaves, system architect at SuperH is presenting a paper on the SoC Evaluation and Design Kit (SEDK). The SEDK is provided to licensees of SuperH and includes the VSIA compliant SuperHyway interconnect and related modelling tools including System C models. The SEDK enables developers to model their SoC design before committing to silicon and includes a modular hardware platform using FPGA technology allowing designers to develop, prototype optimise and debug hardware and related application code.
Dr. Andy Jones, system architecture manager at SuperH is presenting a second paper on the debug capabilities of the SuperH family. Dr Jones will describe the innovative system debug of the SuperH CPU core and SuperHyway interconnect within the overall SoC. This features a SuperHyway bus analyser and the ability to trigger on specific events on the SuperHyway.
The VSI Alliance was founded in 1996 with the aim of promoting IP re-use by creating open standards and specifications that support the integration of software and hardware components from multiple sources.
VSIA members work together to solve the technical barriers to design integration of SoCs by the mix and match of virtual component blocks.
About VSIA
About SuperH, Inc.
SuperH, Inc. develops RISC CPU cores, the SuperHyway on-chip interconnect and software development tools. The SuperHTM family today includes the 32-bit SH-4 and 64-bit SH-5 CPU cores and is ideally suited to multimedia applications that require a single CPU core executing a mix of general purpose code and DSP algorithms. SuperH CPU cores are targeted at consumer, automotive, telecom and handheld multimedia appliance markets with specific emphasis on set top box, residential gateway, car information systems, modems, digital camera and multimedia players.
Further information about SuperH, Inc. and SuperHTM products can be found at www.superh.com
SuperH is a trademark for products originally developed by Hitachi, Ltd. and is owned by Hitachi Ltd.
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