New Xilinx System Generator For DSP V2.3 Tool Enables Lowest Cost, Highest Performance FPGA Designs

Enhanced multiplier macros enable easy development of 285MHz real-time processing systems

SAN JOSE, Calif., November 26, 2002-Xilinx Inc. (NASDAQ: XLNX) today announced that the company is shipping a new version of the industry's most popular DSP design tools for FPGAs - the System Generator for DSP tool v.2.3. The System Generator for DSP tool automatically translates DSP systems developed using MATLAB® and Simulink® from The MathWorks into highly optimized VHDL and IP cores for Xilinx® FPGAs. The new tool gives designers access to pipelined embedded multipliers using pre-placed input and output registers to achieve higher and predictable performance per area of silicon. With the tool's enhanced multipliers, designers can now achieve 285MHz performance independent of device utilization using slower speed grade, low cost Xilinx Virtex-II™ Series FPGAs for DSP implementations. Designers can automatically fit high-performance DSP applications into the most cost-effective Xilinx FPGA.

This new release also supports:

• Three times faster code generation for higher design productivity and lower development costs
• Over a dozen reference designs/tutorials to accelerate the design learning curve
• An application note describing how to create custom DSP data path peripherals for the IBM CoreConnect® bus architecture

"When we started our OptiFusion design, our DSP designers quickly realized that using FPGAs was the only way to achieve the high performance required," commented Jim Waite, director of engineering of Voyan Technology. "However, our DSP designers did not know how to program VHDL, the normal design entry method for FPGAs. Using System Generator for DSP, we were able to explore the design space and automatically create VHDL, test benches and simulation files for ModelSim. The upshot is that we shaved four man months off our design time using the System Generator for DSP tool."

The new System Generator for DSP tool reduces code generation runtime by three times as compared to previous tool versions. Coupled with design compile times of the recently announced Xilinx ISE 5.1 FPGA software, designers now have the industry's most productive "front-to-back" DSP design flow for implementing high-performance DSP systems onto FPGAs. The new System Generator for DSP tool includes a number of reference designs for digital communications and image processing, including a 16-QAM receiver, LMS-based adaptive equalizer, Costas Loop carrier recovery circuit, CORDIC processor, 2-D DWT, image filters, and many more DSP functions and systems. To evaluate these new reference designs, tutorials and the new System Generator for DSP tool visit www.xilinx.com/systemgenerator_dsp to download an evaluation copy.

Additionally, a new application note is available at www.xilinx.com/xapp/xapp264.pdf, describing how the System Generator for DSP tool can create custom DSP data path peripherals for the IBM CoreConnect bus architecture. The application note describes how the bus interface logic can be created, verified, and deployed using the System Generator for DSP tool and recently announced Xilinx Embedded Development Kit (EDK) to run with either a Xilinx MicroBlaze™ soft processor or PowerPC® processor running on Virtex-II Series and Spartan-II™ Series FPGAs. The reference design uses the embedded processor to perform on-line reloading of the DSP data path under the control of an application program running on a host PC.

Xilinx also announced its IP release #1 for ISE 5.1i software. This release allows designers to implement pre-verified, pre-optimized, DSP algorithms in order to finish designs faster and reduce system costs. The new IP release extends the functionality of many existing Xilinx DSP cores such as the MAC, MAC FIR filter and CORDIC cores. The 18x18 multiplier, which features performance rates of 230 MHz in a Virtex-II -6 FPGA and up to 285 MHz in a Virtex-II Pro -7 FPGA, is part of many of these enhanced cores. For information of all cores within this IP core release, see www.xilinx.com/ipcenter.

"Today's high-performance DSP designer is more cost conscious than ever and this new software release we will help our DSP customers retain their competitive edge and profitability in their respective markets," said David Squires, Director of the DSP Center of Excellence at Xilinx.

Price and availability
he new System Generator for DSP v2.3 tool is priced at $1995 if purchased alone or $2495 if purchased together with the Xilinx three-day customer training class entitled "DSP Design Flow for FPGAs." For more information about the new tool, classes, and IP cores, visit: www.xilinx.com/dsp.

Xilinx XtremeDSP Initiative
The Xilinx XtremeDSP™ initiative introduced in 2000, driven by the broadband revolution, addresses the increasing need for high-performance DSP solutions. The initiative represents a major commitment by Xilinx to further establish its leadership as a high-performance DSP solutions provider. The Xilinx DSP solution comprises unique DSP features in its Virtex-II series FPGAs such as up to 556 embedded 18x18 multipliers, over 10 megabits block and distributed memory, pre-engineered DSP algorithms, system-level DSP development tools, and a rapidly growing network of Xilinx AllianceCORE™ and XPERT partners who provide DSP intellectual property cores and design services.

About Xilinx
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic and programmable system solutions. Additional information about Xilinx is available at www.xilinx.com.

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