Codesign tools aren't ready yet for SoC era

Smith said that while some EDA companies offer co-design solutions, true co-design for system-on-chip "still isn't real yet." He said it should become a growth area by 2005.

"What we are seeing today are tools that can do codesign based on models-mapping the hardware and then designing the software," said Smith, who cited Co-Design Automation Inc.'s Superlog as "a tool famous for it. It is excellent software for the embedded silicon world where you are playing with a microcontroller, some logic and flash, but as far as true SoC design, where there are several cores at several stages of the design, it really doesn't work unless you have all the models for those cores because you can't do all the mapping."

By contrast, said Smith, model-based hardware/software co-verification has been around for several years and is fairly mature, with tools offered by Mentor Graphics, Innoveda and Synopsys. But Synopsys is now de-emphasizing its model-based Eaglei co-verification tool while looking to the future with a synthesis-based unified co-design and co-verification flow.

To get to true system-level design, said Smith, requires a high-level synthesis-based solution that doesn't wholly rely on pre-existing models, as today's solutions do, but could generate hardware and software from scripts.

"As long as you get into models, you are playing with a fairly roug h cut on the hardware side," said Smith. "The co-design tools especially are all pretty green."

He said that a high-level synthesis tool added to the existing flow would give users a better idea upfront what is going into hardware, allowing them to use existing co-design tools like Cadence's VCC for better architectural exploration and hardware/software partitioning.

Using co-design and co-verification together efficiently, many agree, requires a system-level design language that can be used by high-level synthesis. Synopsys Inc. has been on the forefront of pushing forward a language called System C and though the language has not yet matured, the company boasts a simulation and a synthesis tool that can use parts of version 1.0 SystemC for limited co-design.

Frank Schirrmeister, director of product management for advanced verification and systems design at Cadence Design Systems Inc., said the EDA industry is trying not to relive the register-transfer-level language w ars. To really drive a system-level flow, he said, will require the industry to back a single language.

"The trick is to find the right representation at the right level of abstraction, which is independent from implementation so you can really make assessments that are not yet bound to a particular implementation," he said. "Right now it feels like the days when there were all these proprietary RT-level languages. The industry needs one language and should not repeat the Verilog vs. VHDL wars."

Smith said that the "software hole" in the co-design/co-verification flow was another issue that must be addressed. While there is a path from system-level and behavioral languages down to RTL, he said, there is no software equivalent to RTL.

While the synthesis-based hardware/software co-design/verification approach is only now growing out of its infancy, Cadence and Mentor are helping to mature the modeling-based approach. Cadence and Mentor said this month that they have created a link between VCC and Mentor's Seamless co-verification tool, incorporating open modeling infrastructures that allow models from VCC to be used down into the Seamless co-verification flow.

In that flow designers explore system-level design in the Cadence VCC environment and confirm architectural decisions, such as the hardware and software partitioning of system functionality. Then, after a series of refinement steps within VCC, the tool exports hardware/software design and testbench infrastructure to Mentor's Seamless, where designers verify the system-level decisions and analyze hardware/software interfaces.

In addition to the Seamless links with VCC, Mentor Graphics is also expanding its role in co-design. The company recently released Platform Express, a tool that uses models of IP platforms. That lets engineers create, configure and verify processor-platform-based, system-on-chip designs (see Aug. 13, page 53).

Serge Leef, general manager of the system-on-chip verification business unit at Mentor, said the company is working on a tool that will take algorithmic descriptions of a particular platform-based SoC and synthesize hardware and software for that particular platform.

Other companies are also exploring ways to enhance their co-verification flow. For example, to speed co-verification, Innoveda has tied its V-CPU product with Axis emulation to speed co-verification (see April 23, page 72).

Methodologies and views
In their Focus reports, users describe methodologies and views of hardware/software co-design and co-verification as it stands today and where it might be going in the future.

ST Microelectronics engineers describe using VCC to create several types of platform models. Mat Newman of Celoxica Ltd. and Stuart Newton of Wind River Systems Inc. team up to describe a methodology for creating an application model.

Motorola engineers describe using Cynergy System Design's Afterburner and ASVP Builder tools in their ASIC process. NEC designers tell how they used Mentor's Seamless to design a disk array subsystem. Finally, another group at ST Microelectronics describes how a CoWare N2C tool was used to design a speech-recognition SoC.