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Tachys Technologies Unveils Ultra-Low Power Dissipation Serial Transceiver Technology With Full-Duplex 3.2 Gbps Throughput
Tachys Technologies Unveils Ultra-Low Power Dissipation Serial Transceiver Technology With Full-Duplex 3.2 Gbps Throughput
Implemented in a .18 CMOS process, the link includes a serdes that transmits and receives data serially over two differential pairs, delivering a programmable, point-to-point full-duplex throughput of 1.0 to 3.2 Gbps, with the ability to run at full speed with less than 100 mW of power dissipation. The serdes embeds on-board clock generators and a programmable pre-emphasizer that counters signal distortion. In addition to the serdes, the technology implements a link-layer flow control mechanism that guarantees lossless transmission and provides backpressure, thus simplifying chipset and system architecture. The technology will be ideal for applications that require chip-to-chip and board-to-board data transmission over printed circuit boards (PCB) or several meters of cabling, and in particular for high-throughput backplane interconnects and switch fabric subsystems found in LAN and WAN switches and concentrators. About Tachys Technologies For further Press information : Tachys Technologies |
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