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Open-Silicon to Demonstrate and Present on Custom SoC Platform Solutions for AI Applications at the TSMC OIP Event in Santa ClaraMILPITAS, Calif., Oct. 01, 2018 -- Open-Silicon, a system-optimized ASIC solution provider and long-standing member of TSMC’s Value Chain Aggregator (VCA) and Design Center Alliance (DCA) programs, will present on custom SoC platform solutions for AI applications at the TSMC Open Innovation Platform® (OIP) Ecosystem Forum on October 3 in Santa Clara, CA. The company will also demonstrate its comprehensive High Bandwidth Memory (HBM2) IP subsystem solution for 2.5D ASICs in TSMC’s FinFET and CoWoS® technologies. What: Open-Silicon’s implementation of a silicon-proven system ASIC platform in TSMC’s FinFET and CoWoS® technologies was initially silicon proven in 16FF+ at 2Gbps data rate, achieving bandwidths up to 256GBps. Keeping up with the ecosystem, the platform quickly evolved to support 2.4Gbps data rate, achieving bandwidths up to >300GBps in 16FFC. Open-Silicon’s next generation platform in 7FF is based on a PPA-optimized HBM2 IP subsystem supporting 3.2Gbps and beyond data rates, achieving bandwidths up to >400GBps. This presentation will discuss the implementation challenges, solutions and methodologies available to minimize risk, optimize performance, and improve 2.5D SiP manufacturing and yield through best-in-class custom silicon solutions. Who: Demonstration: About Open-Silicon
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