OPENEDGES unveils world-first Memory Subsystem IP solution coupling Network-on-Chip (NoC) interconnect with DDR memory controller

October 16, 2018 -- OPENEDGES, the leading IP provider in smart computing, announced its release of cutting-edge ORBIT^TM Memory Subsystem IP solution combining Network-on-Chip (NoC) interconnect and DDR memory controller.

OPENEDGES’ ORBIT^TM DDR Memory Controller IP (OMC^TM) features very high DRAM bandwidth utilization and ultra-low power consumption. And ORBIT^TM Network-on-Chip Interconnect IP (OIC^TM) boasts 2x better performance and 5x lower power consumption than currently available IPs. Either one of the DDR Memory Controller IP or the Network-on-Chip Interconnect IP is licensable independently, but it provides a lot of synergy in terms of performance, power, area, reliability and cost when customers license them together as a complete memory subsystem solution.

Memory bandwidth is becoming a severe bottleneck in SoC performance as new technologies require higher memory bandwidth. Video resolution is moving from full HD to 4K and 8K ultra HD and new applications such as machine learning also demand more and more DRAM bandwidth. One of the most critical issues for AI SoCs is utilizing available DRAM bandwidth efficiently to meet growing performance demand. Moreover, the memory subsystem must stay very reliable at any situation.

Currently one IP vendor provide either one of DDR memory controller or Network-on-Chip interconnect, not both of them. Under such a situation, SoC companies face a lot of challenges in designing high performance and, at the same time, reliable memory subsystem with IPs from independent vendors. OPENEDGES' ORBIT^TM memory subsystem IP solution relieves a lot of burden from SoC companies. From the reliability point of view, the combined IP solution provides system-level support for efficient clock and power management such as clock gating, power gating, DVFS, and so on. In terms of performance, it provides highly effective quality-of-service management feature (ActiveQoS^TM) enabled by tightly-coupled and carefully co-optimized design of the DDR memory controller and the on-chip interconnect. These synergies as a combined memory subsystem IP solution are available from OPENEDGES only.

Sean Lee, the CEO of OPENEDGES, said ‘High-performance Memory Subsystem is an unsung hero for SoC product's success in the market. As new applications are demanding more performance, SoCs have become very hungry for highly efficient but still reliable memory subsystem. In order to overcome these challenges, IP vendors need to have a fresh look at the memory subsystem level requirements beyond just the individual IP level requirements. Our combined ORBIT^TM Memory Subsystem IP solution will help customers to meet tough memory subsystem design challenges in a timely and cost-effective way’.

ORBIT^TM DDR memory controller IP currently supports DDR3, DDR4, LPDDR3, LPDDR4 and LPDDR4x and support of LPDDR5, DDR5, GDDR6 and HBM2 will be available very soon. Both the DDR memory controller IP and the on-chip interconnect IP have been licensed for many SoC companies and already silicon proven. Other than memory subsystem IP, OPENEDGES also provides AI accelerator IP (ENLIGHT^TM), which is also tightly integrated with the memory subsystem IP, and it will be officially released very soon.

About OPENEDGES

OPENEDGES is a semiconductor IP provider for smart computing empowering Internet of Smart Things. Committed to democratizing artificial intelligence technology at the edge devices, OPENEDGES delivers IPs in two key technology areas of smart computing; highly efficient Artificial Intelligence Acceleration and high-performance Memory Subsystem. By synergy of these two technologies, OPENEDGES offers sorely needed boost to performance, efficiency and reliability for Internet of Smart Things. OPENEDGES is backed by many prestigious venture capital companies including Samsung Venture Investment and StoneBridge Ventures. More information about OPENEDGES technology can be found on www.openedges.com.